Computing array based on 1T1R device, operation circuits and operating methods thereof

ABSTRACT

The present invention discloses a computing array based on 1T1R device, operation circuits and operating methods thereof. The computing array has 1T1R arrays and a peripheral circuit; the 1T1R array is configured to achieve operation and storage of an operation result, and the peripheral circuit is configured to transmit data and control signals to control operation and storage processes of the 1T1R arrays; the operation circuits are respectively configured to implement a 1-bit full adder, a multi-bit step-by-step carry adder and optimization design thereof, a 2-bit data selector, a multi-bit carry select adder and a multi-bit pre-calculation adder; and in the operating method corresponding to the operation circuit, initialized resistance states of the 1T1R devices, word line input signals, bit line input signals and source line input signals are controlled to complete corresponding operation and storage processes.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a 371 application of an international PCTapplication serial no. PCT/CN2018/090247, filed on Jun. 7, 2018, whichclaims priority to and the benefit of China Patent Application No.CN201711358553.4, filed on Dec. 17, 2017. The entirety of each of theabove-mentioned patent applications is hereby incorporated by referenceherein and made a part of this specification.

BACKGROUND OF THE INVENTION Technical Field

The present invention belongs to the field of microelectronic devices,and more particularly relates to a computing array based on 1T1R device,operation circuits and operating methods thereof.

Description of the Related Art

In the era of big data, the Moore's Law for integrated circuits, whichimprove the computational performance through the size reduction ofnano-transistor logic devices, has been difficult to continue. Thebottleneck problem of storage and computation separation in thetraditional von Neumann computing architecture is highlighted, and theexisting architecture and hardware cannot meet the demand for superiorcomputing power in explosive growth of information.

Resistive Random Access Memory (RRAM), which has the characteristicssuch as low power consumption, high speed, high integration as well asinformation storage and calculation functions, can break through thelimit of Moore's Law in the development of existing electronic devices,and thus is widely used in improving the speed of computer dataprocessing. In the existing industrial integration technology, RRAM ismainly applied in the 1T1R device structure.

Chinese Patent No. 2014203325960 proposed a non-volatile Boolean logicoperation circuit and an operating method thereof, which realizes acomplete set of non-volatile Boolean logic operations through aback-to-back RRAM structure, but cannot realize circuit cascading,circuit integration and more complex computing functions.

SUMMARY OF THE INVENTION

In view of the above-described defects or improvement requirements inthe art, the present invention provides a computing array based on 1T1Rdevice, operation circuits and operating methods thereof, which aim toachieve a complete set of non-volatile Boolean logic operations, and toachieve more complex computing functions, while improving thecompatibility of the computing circuits and simplifying the operationmethods.

In order to achieve the above objective, according to a first aspect ofthe present invention, there is provided a computing array based on 1T1Rdevice, which comprises: one or more 1T1R arrays and a peripheralcircuit; the 1T1R array is configured to achieve operation and storageof an operation result, and the peripheral circuit is configured totransmit data and control signals to control operation and storageprocesses of the 1T1R arrays.

The 1T1R array includes 1T1R devices arranged in an array, word linesWL, bit lines BL and source lines SL; resistance states of the 1T1Rdevices include: High Resistance H and Low Resistance L; the 1T1Rdevices realize storage and processing of information through differentresistance states; and the 1T1R devices in the same row are connected tothe same word line, the 1T1R devices in the same column are connected tothe same bit line and source line, and through applying differentsignals to the word lines WL, the bit lines BL and the source lines SL,different operations are achieved and operation results are stored.

The 1T1R device includes a transistor and a resistive element; thetransistor includes a substrate, a source, a drain, an insulating layerand a gate, in which the source is connected to the source line SL, andthe gate is connected to the word line WL; the resistive elementincludes two end electrodes, one of which is connected to the bit lineBL and the other of which is connected to the drain of the transistor;and the resistive element has a stacked structure with a nonvolatileresistance transition characteristic.

The resistance state of the 1T1R device can be reversibly transformedunder the stimulation of an applied signal, namely, with the stimulationof an applied signal, the resistance state of the 1T1R device can betransformed from High Resistance to Low Resistance, and with thestimulation of another applied signal, the resistance state of the 1T1Rdevice can be transformed from Low Resistance to High Resistance. Byusing the two resistance states of the 1T1R device, storage andprocessing of information can be achieved.

In a first embodiment of the first aspect of the present invention, theresistive element of the 1T1R device is RRAM; RRAM includes: an upperelectrode, a functional layer and a lower electrode; the upper electrodeis connected to the bit line BL, and the lower electrode is connected tothe drain of the transistor.

The peripheral circuit includes: a state controller, a word linedecoder, a source line decoder, a bit line decoder, a signal amplifier,a control signal modem and a data transmission circuit, wherein:

The state controller has a data input/output terminal Data, an addressinput terminal Address, a clock signal input terminal CLK, a resultinput terminal, a word line output terminal, a bit line output terminal,a source line output terminal and a secondary output terminal; the datainput/output terminal Data of the state controller is configured toinput calculated data on the one hand and output a calculated result onthe other hand, the address input terminal Address of the statecontroller is configured to input address information of a selecteddevice, the clock signal input terminal CLK of the state controller isconfigured to input a clock signal for controlling a calculation timing,and the result input terminal of the state controller is configured toinput a calculated result generated by a pre-stage circuit; the statecontroller generates a control signal according to the input data,address information, clock signal and calculated result, or outputs afinal calculated result.

An input terminal of the word line decoder is connected to the word lineoutput terminal of the state controller, an output terminal of the wordline decoder is connected to a word line of the 1T1R array; the wordline decoder decodes the control signal generated by the statecontroller to obtain a word line control signal, and inputs the wordline control signal to the 1T1R devices through the word line of the1T1R array.

An input terminal of the bit line decoder is connected to the bit lineoutput terminal of the state controller, an output terminal of the bitline decoder is connected to a bit line of the 1T1R array; the bit linedecoder decodes the control signal generated by the state controller toobtain a bit line control signal, and inputs the bit line control signalto the 1T1R devices through the bit line of the 1T1R array.

An input terminal of the source line decoder is connected to the sourceline output terminal of the state controller, an output terminal of thesource line decoder is connected to a source line of the 1T1R array; thesource line decoder decodes the control signal generated by the statecontroller to obtain a source line control signal, and inputs the sourceline control signal to the 1T1R devices through the source line of the1T1R array.

The word line control signal, the bit line control signal and the sourceline control signal are commonly applied to the 1T1R array to controlstates of the 1T1R devices in the 1T1R array.

An input terminal of the signal amplifier is connected to a bit line ofthe 1T1R array; when data information stored in the 1T1R array is read,the signal amplifier converts an acquired resistance signal stored bythe 1T1R device into a voltage signal and then outputs it to the controlsignal modem.

A first input terminal of the control signal modem is connected to thesecondary output terminal of the state controller, a second inputterminal of the control signal modem is connected to an output terminalof the signal amplifier; the control signal modem decodes the controlsignal generated by the state controller to obtain a control signal of anext-stage circuit, or directly transmits the data voltage signal outputby the signal amplifier; the next-stage circuit is the next 1T1R devicein the same 1T1R array, or a next 1T1R array in the compute array.

An input terminal of the data transmission circuit is connected to anoutput terminal of the control signal modem; the data transmissioncircuit feeds back the data voltage signal output by the control signalmodem to the state controller through the result input terminal of thestate controller, or transmits the control signal output from thecontrol signal modem to the word line decoder, the bit line decoder andthe source line decoder of the next-stage circuit.

The data input/output terminal Data, the address input terminal Addressand the clock signal input terminal CLK of the state controllerrespectively serve as a data input/output terminal, an address inputterminal and a clock signal input terminal of the computing array.

In the computing array based on 1T1R device, applied voltage pulses areused as input signals to perform logic operation, and the result of thelogic operation is characterized by the final resistance state of the1T1R device; the result of the logic operation can be non-volatilelystored in the resistance state of the device, the resistance state canbe read by a read signal of a small current (generally at the nanoamperelevel) or a small voltage (generally 0.2V or less), and the resistancesignal can be erased by applying a voltage pulse with a certainamplitude and pulse width.

In the computing array based on 1T1R device, Boolean logic operationsare achieved in the 1T1R devices by applying different voltage pulsesignals to the word lines, source lines and bit lines of the 1T1R array.The initial resistance state of the 1T1R device is defined as a logicsignal I, in which I=0 when the initial resistance state of the 1T1Rdevice is High Resistance, and I=1 when the initial resistance state ofthe 1T1R device is Low Resistance; the word line level voltage isdefined as a logic signal V_(WL), in which V_(WL)=0 when a zero-levelpulse is applied to the word line, and V_(WL)=1 when a forward voltagepulse is applied to the word line; the bit line level voltage is definedas a logic signal V_(BL), in which V_(BL)=0 when a zero-level pulse isapplied to the bit line, and V_(BL)=1 when a forward voltage pulse isapplied to the bit line; the source line level voltage is defined as alogic signal V_(SL), in which V_(SL)=0 when a zero-level pulse isapplied to the source line, and V_(SL)=1 when a forward voltage pulse isapplied to the source line; the result of the logical operation in the1T1R device is non-volatilely stored in the 1T1R device, and wheninformation stored in the 1T1R device is read, the resistance state ofthe 1T1R device is defined as a logic signal R, in which R=0 when theresistance state of the 1T1R device is High Resistance, and R=1 when theresistance state of the 1T1R device is Low Resistance; and a logicalrelationship between the logic signal I, the logic signal V_(WL), thelogic signal V_(BL), the logic signal V_(SL), and the logic signal R is:R=I· V _(WL) +I·V _(WL) ·V _(BL) +I·V _(WL)· V _(BL) · V _(SL) +Ī·V_(WL) ·V _(BL)· V _(ST)

In the computing array based on 1T1R device, Boolean logic operation areimplemented in a single 1T1R device, and specifically, the operatingmethod includes the following steps.

(1) Initializing the 1T1R device to obtain a logic signal I.

(2) Respectively applying a voltage pulse signal to a word line, asource line and a bit line to obtain a logic signal V_(WL), a logicsignal V_(SL) and a logic signal V_(BL).

(3) Reading a result of the logical operation, that is, a logic signalR.

By controlling values of the logic signals I, V_(WL), V_(BL) and V_(SL),the following 16 Boolean logic operations can be implemented:

implementation of logic 0: I=0, V_(WL)=0, V_(BL)=p and V_(SL)=q;

implementation of logic 1: I=1, V_(WL)=0, V_(BL)=p and V_(SL)=q;

implementation of p logic: I=p, V_(WL)=0, V_(BL)=0 and V_(SL)=q;

implementation of p logic: I=q, V_(WL)=0, V_(BL)=0 and V_(SL)=p;

implementation of p logic: I=p, V_(WL)=0, V_(BL)=p and V_(SL)=q;

implementation of q logic: I=q, V_(WL)=0, V_(BL)=p and V_(SL)=q;

implementation of p+q logic: I=p, V_(WL)=1, V_(BL)=p and V_(SL)=0;

implementation of p+q logic: I=1, V_(WL)=p, V_(BL)=0 and V_(SL)=q;

implementation of p·q logic: I=0, V_(WL)=p, V_(BL)=q and V_(SL)=0;

implementation of p·q logic: I=q, V_(WL)=p, V_(BL)=q and V_(SL)=1;

implementation of p+q logic: I=1, V_(WL)=1, V_(BL)=p and V_(SL)=q;

implementation of p+q logic: I=1, V_(WL)=p, V_(BL)=q and V_(SL)=1;

implementation of p·q logic: I=q, V_(WL)=1, V_(BL)=0 and V_(SL)=p;

implementation of p·q logic: I=p, V_(WL)=1, V_(BL)=0 and V_(SL)=q;

implementation of p·q+p·q logic: I=p, V_(WL)=q, V_(BL)=p and V_(SL)=p;and

implementation of p·q+p·q logic: I=q, V_(WL)=p, V_(BL)=q and V_(SL)=q.

Further, by inputting a logic signal V_(WL)=1 via the word line, a logicsignal V_(BL)=V_(read) via the bit line and a logic signal V_(SL)=0 viathe source line, the logic signal stored in the 1T1R device can be read,in which V_(read) is a voltage pulse signal applied when the resistancestate of the 1T1R device is read.

In the present invention, symbols similar to I, V_(WL), V_(BL) andV_(SL) are used to denote logical signals with the same concept, andsignals corresponding to different 1T1R devices are distinguished onlyby different subscripts

According to a second aspect of the present invention, there is providedan operation circuit based on the computing array for implementing a1-bit full adder, in which a sum s₀ and a high-order carry c₁ arecalculated according to a logic signal a, a logic signal b and alow-order carry c₀ that are input; the operation circuit comprises: a1T1R array A₁, a 1T1R array A₂ and a 1T1R array A₃; the 1T1R array A₁includes a 1T1R device R_(b) for calculating and storing intermediatedata s₀*, a word line signal corresponding to R_(b) is V_(WLb), a bitline signal corresponding to R_(b) is V_(BLb) and a source line signalcorresponding to R_(b) is V_(SLb); the 1T1R array A₂ includes a 1T1Rdevice R_(c) for calculating and storing the high-order carry c₁, a wordline signal corresponding to R_(c) is Y_(WLc), a bit line signalcorresponding to R_(c) is V_(BLc) and a source line signal correspondingto R_(c) is V_(SLc); the 1T1R array A₃ includes a 1T1R device R_(s) forcalculating and storing the sum s₀, a word line signal corresponding toR_(s) is V_(WLs), a bit line signal corresponding to R_(s) is V_(BLs)and a source line signal corresponding to R_(s) is V_(SLs); and theintermediate data s₀* calculated by the 1T1R array A₁ and the high-ordercarry c₁ calculated by the 1T1R array A₂ are converted by the signalamplifier and the control signal modem, and then transmitted to the 1T1Rarray A₃ through the data transmission circuit.

In conjunction with the second aspect of the present invention, thepresent invention further provides an operating method based on theoperation circuit, which comprises:

(S1-1) Inputting logic signals V_(WLc)=1, V_(BLc)=c₀ and V_(SLc)=c₀ towrite the input logic signal c₀ into R_(c) of the 1T1R array A₂;inputting logic signals V_(WLb)=1, V_(BLb)=a₀ and V_(SLb)=a₀ to writethe input logic signal a₀ into R_(b) of the 1T1R array A₁; inputtinglogic signals V_(WLs)=1, V_(BLs)=a₀ and V_(SLs)=a₀ to write the inputlogic signal a₀ into R_(s) of the 1T1R array A₃.

(S1-2) Inputting logic signals V_(WLc)=1, V_(BLc)=a₀ and V_(SLc)=b₀ tocalculate a high-order carry c₁=a₀·b₀+a₀·c₀+c₀·b₀ and store c₁ in R_(c)of the 1T1R array A₂; inputting logic signals V_(WLb)=b₀, V_(BLb)=a₀ andV_(SLb)=a₀ to calculate an intermediate result s₀*=a₀⊕b₀ and store s₀*in R_(b) of the 1T1R array A₁; inputting logic signals V_(WLs)=b₀,V_(BLs)=a₀ and V_(SLs)=a₀ to calculate an intermediate result s₀* andstore s₀* in R_(s) of the 1T1R array A₃.

(S1-3) Reading the logic signal c₁ stored in R_(c) of the 1T1R array A₂;reading the logic signal s₀ stored in R_(b) of the 1T1R array A₁;inputting logic signals V_(WLs)=c₀, V_(BLs)=s₀* and V_(SLs)=s₀* tocalculate a sum s₀=a₀⊕b₀⊕c₀ and store s₀ in R_(s) of the 1T1R array A₃.

(S1-4) reading the logic signal s₀ stored in R_(s) of the 1T1R array A₃.

According to a third aspect of the present invention, there is providedan operation circuit based on the computing array for implementing amulti-bit step-by-step carry adder, in which sums s_(0˜n−1) and carryinformation c_(n) are calculated according to input data a_(0˜n−1) andb_(0˜n−1) and carry information c₀, and n represents the number of bitsof the operation data, the operation circuit comprises: a 1T1R array D₁,a 1T1R array D₂ and a 1T1R array D₃; the 1T1R array D₁ includes n 1T1Rdevices R_(0b)˜R_((n−1)b) for calculating and storing intermediateresults s_(0˜n−1)*, word line control signals corresponding toR_(0b)˜R_((n−1)b) are respectively V_(WL0b)˜V_(WL(n−1)b), bit linecontrol signals corresponding to R_(0b)˜R_((n−1)b) are respectivelyV_(BL0b)˜V_(BL(n−1)b), and source line control signals corresponding toR_(0b)˜R_((n−1)b) are respectively V_(SL0b)˜V_(SL(n−1)b); the 1T1R arrayD₁ is used for data backup; the 1T1R array D₂ includes a 1T1R deviceR_(n) for calculating and storing carry data c_(i) (i is an integer from0 to 8), a word line control signal corresponding to R_(n) is V_(WLn), abit line control signal corresponding to R_(n) is V_(BLn) and a sourceline control signal corresponding to R_(n) is V_(SLn); the 1T1R array D₃includes n 1T1R devices R₀˜R_(n−1) for calculating and storing additionoperation results s_(0˜-n−1), word line control signals corresponding toR₀˜R_(n−1) are respectively V_(WL0)˜V_(WL(n−1)), bit line controlsignals corresponding to R₀˜R_(n−1) are respectivelyV_(BL0b)˜V_(BL(n−1)), and source line control signals corresponding toR₀˜R_(n−1) are respectively V_(SL0)˜V_(SL(n−1)); and the intermediatedata s_(0˜n−1)* calculated by the 1T1R array D₁ and the carryinformation c_(i) calculated by the 1T1R array D₂ are converted by thesignal amplifier and the control signal modem, and then transmitted tothe 1T1R array D₃ through the data transmission circuit.

In conjunction with the third aspect of the present invention, thepresent invention further provides an operating method based on theoperation circuit, which comprises:

(S2-1) Inputting logic signals V_(WL0˜(n−1))=1, V_(BL0˜(n−1))=a_(0˜n−1)and V_(SL0˜(n−1))=a_(0˜n−1) to write the input data a_(0˜n−1) intoR_(0˜n−1) of the 1T1R array D₃; inputting logic signals V_(WLn)=1,V_(BLn)=c₀ and V_(SLn)=c₀ to write the carry information c₀ into R_(n)of the 1T1R array D₂, a word line input signal, a bit line input signaland a source line input signal of the 1T1R array D₁ being the same asthat of the 1T1R array D₃.

(S2-2) Inputting logic signals V_(WL0˜(n−1))=b_(0˜n−1),V_(BL0˜(n−1))=a_(0˜n−1) and V_(SL0˜(n−1))=a_(0˜n−1) to calculateintermediate results s_(0˜n−1)=a_(0˜n−1)⊕b_(0˜n−1) and store s_(0˜n−1)*in R_(0˜n−1) of the 1T1R array D₃; inputting logic signalsV_(WL0b˜(n−1)b)=b_(0˜n−1), V_(BL0b˜(n−1)b)=a_(0˜n−1) andV_(SL0b˜(n−1)b)=a_(0˜n−1) to calculate intermediate results s_(0˜n−1)*and store s_(0˜n−1)* in R_(0b˜(n−1)b), of the 1T1R array D₁; inputtinglogic signals V_(WLn)=1, V_(BLn)=a₀ and V_(SLn)=b₀ to calculatec₁=a₀·b₀+a₀·c₀+c₀·b₀ and store c₁ in R_(n) of the 1T1R array D₂.

(S2-3) Reading s₀* from R_(0b) of the 1T1R array D₁, and reading s₁*from R_(1b) of the 1T1R array D1; inputting logic signals V_(WL0)=c₀,V_(WL1)=c₁, V_(WL2˜n−1)=0, V_(BL0)=s₀*, V_(BL1)=s₁*, V_(BL2˜n−1)=0,V_(SL0)=s₀*, V_(SL1)=s₁* and V_(SL2˜n−1)=0 to calculate s₀=a₀⊕b₀⊕c₀ ands₁=a₁⊕b₁⊕c₁, and store s₀ in R₀ of the 1T1R array D₃ and s₁ in R₁ of the1T1R array D₃.

(S2-4) Denoting the i-th bit in the operation data or operation resultby i, and giving i an initial value of i=2.

(S2-5) Inputting logic signals V_(WLn)=1, V_(BLn)=a_(i−1) andV_(SLn)=b_(i−1) to calculatec_(i)=a_(i−1)·b_(i−1)+a_(i−1)·c_(i−1)+c_(i−1)·b_(i−1) and store c_(i) inR_(n) of the 1T1R array D₂.

(S2-6) Reading s_(i)* from R_(ib) of the 1T1R array D₁; inputting logicsignals V_(WL0˜(i−1))=0, V_(WLi)=c_(i), V_(WL(i+1)˜(n−1))=0,V_(BL0˜(i−1))=0, V_(BLi)=s_(i)* , V_(BL(i+1)˜(n−1))=0, V_(SL0˜(i−1))=0,V_(SL1)=s_(i)* and V_(SL(i+1)˜(n−1))=0 to calculates_(i)=a_(i)⊕b_(i)⊕c_(i) and store s_(i) in R_(i) of the 1T1R array D₃.

(S2-7) Incrementing the value of i by 1, and if i<n−1, proceeding to thestep (S2-5); otherwise, proceeding to step (S2-8).

(S2-8) Inputting logic signals V_(WLn)=1, V_(BLn)=a_(n−2) andV_(SLn)=b_(n−2) to calculatec_(n−1)=a_(n−2)·b_(n−2)+a_(n−2)·c_(n−2)+c_(n−2)·b_(n−2) and storec_(n−1) in R_(n) of the 1T1R array D₂.

(S2-9) Reading s_((n−1))* from R_((n−1)b) of the 1T1R array D₁;inputting logic signals V_(WL0˜(n−2))=0, V_(WL(n−1))=c_(n−1),V_(BL0˜(n−2))=0, V_(BL(n−1))=s_(n−1)*, V_(SL0˜(n−2))=0 andV_(SL(n−1))=s_(n−1)* to calculate s_(n−1)=a_(n−1)⊕b_(n−1)⊕c_(n−1) andstore s_(n−1) in R_(n−1) of the 1T1R array D₃.

(S2-10) inputting logic signals V_(WLn)=1, V_(BLn)=a_(n−1) andV_(SLn)=b_(n−1) to calculatec_(n)=a_(n−1)·b_(n−1)+a_(n−1)·c_(n−1)+c_(n−1)·b_(n−1) and store c_(n) inR_(n) of the 1T1R array D₂.

According to a fourth aspect of the present invention, there is providedan operation circuit based on the computing array for implementing anoptimized multi-bit step-by-step carry adder, in which sums s_(0˜n−1)and carry information c_(n) are calculated according to input dataa_(0˜n−1) and b_(0˜n−1) and carry information c₀, and n represents thenumber of bits of the operation data; the operation circuit comprises: a1T1R array E₁, a 1T1R array E₂ and a 1T1R array E₃; the 1T1R array E₁includes n 1T1R devices R_(0b)˜R_((n−1)b) for calculating and storingdata s_(0˜n−1)*, word line control signals corresponding toR_(0b)˜R_((n−1)b) are respectively V_(WL0b)˜V_(WL(n−1)b), bit linecontrol signals corresponding to R_(0b)˜R_((n−1)b) are respectivelyV_(BL0b)˜V_(BL(n−1)b), and source line control signals corresponding toR_(0b)˜R_((n−1)b) are respectively V_(SL0b)˜V_(SL(n−1)b); the 1T1R arrayE₁ is used for data backup; the 1T1R array E₂ includes (n+1) 1T1Rdevices R_(0c)˜R_(nc) for calculating and storing carry data c_(i) (i isan integer from 0 to n), word line control signals corresponding toR_(0c)˜R_(nc) are respectively V_(WL0c)˜V_(WLnc), bit line controlsignals corresponding to R_(0c)˜R_(nc) are respectivelyV_(BL0c)˜V_(BLnc), and source line control signals corresponding toR_(0c)˜R_(nc) are respectively V_(SL0c)˜V_(SLnc); the 1T1R array E₃includes n 1T1R devices R₀˜R_(n−1) for calculating and storing additionoperation results s_(0˜n−1), word line control signals corresponding toR₀˜R_(n−1) are respectively V_(WL0)˜V_(WL(n−1)), bit line controlsignals corresponding to R₀˜R_(n−1) are respectivelyV_(BL0)˜V_(BL(n−1)), and source line control signals corresponding toR₀˜R_(n−1) are respectively V_(SL0)˜V_(SL(n−1)); and the intermediatedata s_(0˜n−1)* calculated by the 1T1R array E₁ and the carryinformation c_(i) calculated by the 1T1R array E₂ are converted by thesignal amplifier and the control signal modem, and then transmitted tothe 1T1R array E₃ through the data transmission circuit.

In conjunction with the fourth aspect of the present invention, thepresent invention further provides an operating method based on theoperation circuit, which comprises:

(S3-1) Inputting logic signals V_(WL0˜(n−1))=1, V_(BL0˜(n−1))=a_(0˜n−1)and V_(SL0˜(n−1))=a_(0˜n−1) to write the input operational dataa_(0˜n−1) into R_(0˜n−1) of the 1T1R array E₃; inputting logic signalsV_(WL0b˜(n−1)b)=1, V_(BL0b˜(n−1)b)=a_(0˜n−1) andV_(SL0b˜(n−1)b)=a_(0˜n−1) to write the input operational data a_(0˜n−1)into R_(0b˜(n−1)b) of the 1T1R array E₁; inputting logic signalsV_(WL0c˜nc)=1, V_(BL0c˜nc)=c₀ and V_(SL0c˜nc)=c₀ to write the carryinformation c₀ into R_(0c˜nc) of the 1T1R array E₂.

(S3-2) Inputting logic signals V_(WL0˜(n−1))=b_(0˜n−1),V_(BL0˜(n−1))=a_(0˜n−1) and V_(SL0˜(n−1))=a_(0˜n−1) to calculateintermediate results s_(0˜n−1)*=a_(0˜n−1)⊕b_(0˜n−1) and store s_(0˜n−1)*in R_(0˜n−1) of the 1T1R array E₃; inputting logic signalsV_(WL0b˜(n−1)b)=b_(0˜n−1), V_(BL0b˜(n−1)b)=a_(0˜n−1) andV_(SL0b˜(n−1)b)=a_(0˜n−1) to calculate intermediate results s_(0˜n−1)*and store s_(0˜n−1) in R_(0b˜(n−1)b) of the 1T1R array E₁; inputtinglogic signals V_(WL0c)=0, V_(WL1c˜nc)=1, V_(BL0c˜nc)=a₀ andV_(SL0c˜nc)=b₀ to calculate c₁=a₀·b₀+a₀·c₀+c₀·b₀ and store c₁ inR_(1c˜nc) of the 1T1R array E₂.

(S3-3) Reading s₀* from R_(0b) of the 1T1R array E₁, and reading s₁*from R_(1b) of the 1T1R array E1; inputting logic signals V_(WL0)=c₀,V_(WL1)=c₁, V_(WL2˜(n−1))=0, V_(BL0)=s₀*, V_(BL1)=s₁*, V_(BL2˜(n−1))=0,V_(SL0)=s₀*, V_(SL1)=s₁* and V_(SL2˜(n−1))=0 to calculate s₀=a₀⊕b₀⊕c₀and s₁=a₁⊕b₁⊕c₁, and store s₀ in R₀ of the 1T1R array E₃ and s₁ in R₁ ofthe 1T1R array E₃; inputting logic signals V_(WL0c˜1c)=0, V_(WL2˜nc)=1,V_(BL0˜nc)=a₁ and V_(SL0c˜nc)=b₁ to calculate c₂=a₁·b₁+a₁·c₁+c₁·b₁ andstore c₂ in R_(2c˜nc) of the 1T1R array E₂.

(S3-4) Denoting the i-th bit in the operation data or operation resultby i, and giving i an initial value of i=2.

(S3-5) Reading s_(i)* from R_(ib) of the 1T1R array E₁; inputting logicsignals V_(WL0˜(i−1))=0, V_(WLi)=c_(i), V_(WL(i+1)˜(n−1))=0,V_(BL0˜(i−1))=0, V_(BLi)=s_(i)*, V_(BL(i+1)˜(n−1))=0, V_(SL0˜(i−1))=0,V_(SLi)=s_(i)* and V_(SL(i+1)˜(n−1))=0 to calculates_(i)=a_(i)⊕b_(i)⊕c_(i), and store s_(i) in R_(i) of the 1T1R array E₃;inputting logic signals V_(WL0c˜ic)=0, V_(WL(i+1)c˜nc)=1,V_(BL0c˜nc)=a_(i) and V_(SL0c˜nc)=b_(i) to calculatec_(i+i)=a_(i)·b_(i)+a_(i)·c_(i)+c_(i)·b_(i) and store c_(i+1) inR_((i+1)c˜nc) of the 1T1R array E₂.

(S3-6) Incrementing the value of i by 1, and if i<n−1, proceeding to thestep (S3-5); otherwise, proceeding to a step (S3-7).

(3-7) Reading s_(n−1)* from R_((n−1)b) the 1T1R array E₁; inputtinglogic signals V_(WL0˜(n−2))=0, V_(WL(n−1))=c_(n−1), V_(BL0˜(n−2))=0,V_(BL(n−1))=s_(n−1) *, V_(SL0˜(n−2))=0 and V_(SL(n−1))=s_(n−1)* tocalculate s_(n−1)=a_(n−1)⊕b_(n−1)⊕c_(n−1) and store s_(n−1) in R_(n−1)of the 1T1R array E₃; and inputting logic signals V_(WL0c˜(n−1)c)=0,V_(WLnc)=1, Y_(BL0c˜nc)=a_(n−1) and V_(SL0c˜nc)=b_(n−i) to calculatec_(n)=a_(n−1)·b_(n−1)+a_(n−1)·c_(n−1)+c_(n−1)·b_(n−1) and store c_(n) inR_(nc) of the 1T1R array E₂.

According to a fifth aspect of the present invention, there is providedan operation circuit based on the computing array for implementing a2-bit data selector, in which a logic signal a, a logic signal b and acontrol signal Sel are input to output the logic signal a or the logicsignal b by controlling a value of the control signal Sel; the operationcircuit comprises: a 1T1R array F, wherein the 1T1R array F includes one1T1R device R, a word line signal corresponding to R is V_(WL), a bitline signal corresponding to R is V_(BL), and a source line signalcorresponding to R is V_(SL).

In conjunction with the fifth aspect of the present invention, thepresent invention further provides an operating method based on theoperation circuit, which comprises:

(S4-1) Inputting logic signals V_(WL)=1, V_(BL)=a and V_(SL)=ā toinitialize the 1T1R device R, and write the input logic signal an into Rof the 1T1R array F.

(S4-2) Inputting logic signals V_(WL)=Sel, V_(BL)=b and V_(SL)=b toinput the logic signal b and the control signal Sel so as to select anoutput logic signal out,

wherein the logic signal a and the logic signal b represent only twoindependent logic signals; when the control signal Sel=0, the outputsignal out=a; and when the control signal Sel=1, the output signalout=b.

According to a sixth aspect of the present invention, there is providedan operation circuit based on the computing array for implementing amulti-bit carry select adder, in which sums s_(0˜n−1) and carryinformation c_(n) are calculated according to input data a_(0˜n−1) andb_(0˜n−1) and carry information c₀, n represents the number of bits ofthe operation data, and in the calculation process, according to thecarry information of each bit, an XNOR operation result or an XORoperation result of the corresponding bit of the operation data isselected as bit information of the sum; the operation circuit comprises:a 1T1R array G₁, a 1T1R array G₂ and a 1T1R array G₃; the 1T1R array G₁includes n 1T1R devices R_(0x)˜R_((n−1)x) for calculating and storingXNOR operation results of data a_(0˜n−1) and b_(0˜n−1)(X_(0˜n−1)=a_(0˜n−1) XNOR b_(0˜n−1)), word line control signalscorresponding to R_(0x)˜R_((n−1)x) are respectivelyV_(WL0x)˜V_(WL(n−1)x), bit line control signals corresponding toR_(0x)˜R_((n−1)x) are respectively V_(BL0x)˜V_(BL(n−1)x), and sourceline control signals corresponding to R_(0x)˜R_((n−1)x) are respectivelyV_(SL0x)˜V_(SL(n−1)x); the 1T1R array G₂ includes (n+1) 1T1R devicesR_(0c)˜R_(nc) for calculating carry data c_(i) (i is an integer from 0to n), word line control signals corresponding to R_(0c)˜R_(nc) arerespectively V_(WL0x)˜V_(WLnc), bit line control signals correspondingto R_(0c)˜R_(nc) are respectively V_(BL0c)˜V_(BLnc), and source linecontrol signals corresponding to R_(0c)˜R_(nc) are respectivelyV_(SL0c)˜V_(SLnc); the 1T1R array G₃ includes n 1T1R devices R₀˜R_(n−1)for calculating and storing addition operation results s_(0˜n−1), wordline control signals corresponding to R₀˜R_(n−1) are respectivelyV_(WL0)˜V_(WL(n−1)), bit line control signals corresponding toR₀˜R_(n−1) are respectively V_(BL0)-V_(BL(n−1)), and source line controlsignals corresponding to R₀˜R_(n−1) are respectivelyV_(SL0)-V_(SL(n−1)); and the XNOR operation results X_(0˜n−1) calculatedby the 1T1R array G₁ and the carry information c_(i) calculated by the1T1R array G₂ are converted by the signal amplifier and the controlsignal modem, and then transmitted to the 1T1R array G₃ through the datatransmission circuit.

In conjunction with the sixth aspect of the present invention, thepresent invention further provides an operating method based on theoperation circuit, which comprises:

(S5-1) Inputting logic signals V_(WL0x˜(n−1)x)=1,V_(BL0x˜(n−1)x)=b_(0˜n−1) and V_(SL0x˜(n−1)x)=b_(0˜n−1) to store theresult b_(0˜n−1) of inverting the input operation data b_(0˜n−1) inR_(0x˜nc)=c₀ of the 1T1R array G1; inputting logic signalsV_(WL0c˜nc)=1, V_(BL0c˜nc)=c₀ and V_(SL0c˜nc)=c₀ to store c₀ inR_(0c˜nc) of the 1T1R array G₂; inputting logic signals V_(WL0˜(n−1))=1,V_(BL0˜(n−1))=a_(0˜n−1) and V_(SL0˜(n−1))=a_(0˜n−1) to store the inputoperational data a_(0˜n−1) in R_(0˜n−1) of the 1T1R array G₃.

(S5-2) Inputting logic signals V_(WL0x˜(n−1)x)=a_(0˜n−1),V_(BL0x˜(n−1)x)=b_(0˜n−1) and V_(SL0x˜(n−1)x)=b_(0˜n−1) to calculateXNOR operation results of the calculated data a_(0˜n−1) and b_(0˜n−1)(X_(0˜n−1)=a_(0˜n−1) XNOR b_(0˜n−1)) and store X_(0˜n−1) inR_(0x˜(n−1)x) of the 1T1R array G₁; inputting logic signals V_(WL0c)=0,V_(WL1c˜nc)=1, V_(BL0c˜nc)=a₀ and V_(SL0c˜nc)=b₀ to calculatec₁=a₀·b₀+a₀·c₀+c₀·b₀ and store c₁ in R_(1c˜nc) of the 1T1R array G₂;inputting logic signals V_(WL0x˜(n−1))=b_(0˜n−1),V_(BL0x˜(n−1))=a_(0˜n−1) and V_(SL0x˜(n−1))=a_(0˜n−1) , to calculate XORoperation results s_(0˜n−1)*=a_(0˜n−1)⊕b_(0˜n−1) and store s_(0˜n−1)* inR_(0˜n−1) of the 1T1R array G₃.

(S5-3) Inputting logic signals V_(WL0c˜1c)=0, V_(WL2c˜nc)=1,V_(BL0c˜nc)=a₁ and V_(SL0c˜nc)=b₁ to calculate c₂=a₁·b₁+a₁·c₁+c₁·b₁ andstore c₂ in R_(2c˜nc) of the 1T1R array G₂; inputting logic signalsV_(WL0)=c₀, V_(WL1)=c₁, V_(WL2˜(n−1))=0, V_(BL0˜(n−1))=X_(0˜n−1) andV_(SL0˜(n−1))=X_(0˜n−1) to calculate s₀ and s₁, and store s₀ in R₀ ofthe 1T1R array G₃ and s₁ in R₁ of the 1T1R array G₃; when c₀=0,s₀=a₀⊕b₀, and when c₁=0, s₀=a₀⊕b₀ ; when c₁=0, s₁=a₁⊕b₁, and when c₁=1,s₁=a₁⊕b₁ .

(S5-4) Denoting the i-th bit in the operation data or operation resultby i, and giving i an initial value of i=2.

(S5-5) Inputting logic signals V_(WL0c˜ic)=0, V_(WL(i+1)c˜nc)=1,V_(BL0c˜nc)=a_(i) and V_(SL0c˜nc)=b_(i) to calculatec_(i+1)=a_(i)·b_(i)+a_(i)·c_(i)+c_(i)·b_(i) and store c_(i+1) inR_((i+1)c˜nc) of the 1T1R array G₂; inputting logic signalsV_(WL0x˜(i−1))=0, V_(WLi)=c_(i), V_(WL(i+1)˜(n−1)=)0,V_(BL0˜(n−1))=X_(0˜n−1) and V_(SL0˜(n−1))=X_(0˜n−1) to calculate s_(i)and store s_(i) in R_(i) of the 1T1R array G₃; when c_(i)=0,s_(i)=a_(i)⊕b_(i), and when c_(i)=1, s_(i)=a_(i)⊕b_(i) .

(S5-6) Incrementing the value of i by 1, and if i<n−1, proceeding to thestep (S5-5); otherwise, proceeding to a step (S5-7).

(S5-7) Inputting logic signals V_(WL0c˜(n−1)c)=0, V_(WLnc)=1,V_(BL0c˜nc)=a_(n−1) and V_(SL0c˜nc)=b_(n−1) to calculatec_(n)=a_(n−1)·b_(n−1)+a_(n−1)·c_(n−1)+c_(n−1)·b_(n−1) and store c_(n) inR_(nc) of the 1T1R array G₂; inputting logic signals V_(WL0˜(n−2))=0,V_(WL(n−1))=c_(n−1), V_(BL0˜(n−1))=X_(0˜n−1) and V_(SL0˜(n−1))=X_(0˜n−1)to calculate s_(n−1) and store s_(n−1) in R_(n−1) of the 1T1R array G₃;when n_(n−1)=0, s_(n−1)=a_(n−1)⊕b_(n−1), and when c_(n−1)=1,s₇=a_(n−1)⊕b_(n−1) .

According to a seventh aspect of the present invention, there isprovided an operation circuit based on the computing array forimplementing a multi-bit pre-calculation adder, in which sums s_(0˜n−1)and carry information c_(n) are calculated according to input dataa_(0˜n−1) and b_(˜n−1) and carry information c₀, and n represents thenumber of bits of the operation data; the operation circuit comprises: a1T1R array H₁ and a 1T1R array Hz; the 1T1R array H₁ includes (n+1) 1T1Rdevices R_(0c)˜R_(nc) for calculating carry data c_(i) (i is an integerfrom 0 to n), word line control signals corresponding to R_(0c)˜R_(nc)are respectively V_(WL0c)˜V_(WLnc), bit line control signalscorresponding to R_(0c)˜R_(nc) are respectively V_(BL0c)˜V_(BLnc), andsource line control signals corresponding to R_(0c)˜R_(nc) arerespectively V_(SL0c)˜V_(SLnc); the 1T1R array H₂ includes n 1T1Rdevices R₀˜R_(n−1) for calculating and storing addition operationresults s_(0˜n−1), word line control signals corresponding to R₀˜R_(n−1)are respectively V_(WL0)˜V_(WL(n−1)), bit line control signalscorresponding to R₀˜R_(n−1) are respectively V_(BL0)˜V_(BL(n−1)), andsource line control signals corresponding to R₀˜R_(n−1) are respectivelyV_(SL0)˜V_(SL(n−1)); and the carry information c_(i) calculated by the1T1R array H₁ is converted by the signal amplifier and the controlsignal modem, and then transmitted to the 1T1R array H₂ through the datatransmission circuit.

In conjunction with the seventh aspect of the present invention, thepresent invention further provides an operating method based on theoperation circuit, which comprises:

(S6-1) Inputting logic signals V_(WL0c˜nc)=1, V_(BL0c˜nc)=c₀ andV_(SL0c˜nc)=c₀ to store c₀ in R_(0c˜nc) of the 1T1R array H₁; inputtinglogic signals V_(WL0˜(n−1))=1, V_(BL0˜(n−1))=c₀ and V_(SL0˜(n−1))=c₀ tostore the input carry information c₀ in R_(0˜n−1) of the 1T1R array H₂.

(S6-2) Inputting logic signals V_(WL0c)=0, V_(WL1c˜nc)=1, V_(BL0c˜nc)=a₀and V_(SL0c˜nc)=b₀ to calculate c₁=a₀·b₀+a₀·c₀+c₀·b₀ and store c₁ inR_(1c˜nc) of the 1T1R array H₁; inputting logic signals V_(WL0˜(n−1))=1,V_(BL0˜(n−1))=a₀, V_(SL0)=b₀ and V_(SL1˜(n−1))=b₀ to calculates₀′=c₀·a₀+c₀ ·a₀·b₀ +c₀·a₀ ·b₀ and c₁=a₀·b₀+a₀·c₀+c₀·b₀, and store s₀′in R₀ of the 1T1R array H₂ and c₁ in R_(1˜n−1) of the 1T1R array H₂.

(S6-3) Inputting logic signals V_(WL0c˜1c)=0, V_(WL2c˜nc)=1,V_(BL0c˜nc)a₁ and V_(SL0c˜nc)=b₁ , to calculate c₂=a₁·b₁+a₁·c₁+c₁·b₁ andstore c₂ in R_(2c˜nc) of the 1T1R array H₁; inputting logic signalsV_(WL0˜(n−1))=1, V_(BL0)=b₀, V_(BL1˜(n−1))=a₁, V_(SL0)=c₁, V_(SL1)=b₁and V_(SL2˜(n−1))=b₁ to calculate s₀=a₀⊕b₀⊕c₀, s₁=c₁·a₁+c₁ ·a₁·b₁ +c₁ a₁·b₁ and c₂=a₁·b₁+a₁·c₁+c₁·b₁, and store s₀ in R₀ of the 1T1R array H₂,s₁ in R₁ of the 1T1R array H₂ and c₂ in R_(2˜(n−1)) of the 1T1R arrayH₂.

(S6-4) Denoting the i-th bit in the operation data or operation resultby i, and giving i an initial value of i=1.

(S6-5) Inputting logic signals V_(WL0c˜(i+1)c)0, V_(WL(i+2)c˜nc)=1,V_(BL0c˜nc)=a_(i+1) and V_(SL0c˜nc)=b_(i+1) to calculatec_(i+2)=a_(i+1)·b_(i+1)+a_(i+1)·c_(i+1)+c_(i+1)·b_(i+1) and storec_(i+2) in R_((i+2)c˜nc) of the 1T1R array H₁; inputting logic signalsV_(WL0˜(i−1))=0, V_(WLi˜(n−1))=1, V_(BL0˜(i−1))=0, V_(BLi)=b_(i),V_(BL(i+1)˜(n−1))a_(i+1), V_(SL0˜(i−1))0, V_(SLi)=c_(i+1),V_(SL(i+1))b_((i+1)) and V_(SL(i+2)˜(n−1)) b_(i+1) to calculates_(i)=a_(i)⊕b_(i)⊕c_(i), s_(i+1)=c_(i+1)·a_(i+1)+c_(i+1) ·a_(i+1)b_(i+1) +c_(i+1)·a_(i+1) ·bc_(i+1) , andc_(i+2)=a_(i+1)·b_(i+1)+a_(i+1)·c_(i+1)+c_(i+1)·b_(i+1) and store s_(i)in R₁ of the 1T1R array H₂, s_(i+1) in R_(i+1) of the 1T1R array H₂ andc_(i+2) in R_((i+2)˜(n−1)) of the 1T1R array H₂.

(S6-6) Incrementing the value of i by 1, and if i<n−1, proceeding to thestep (S6-5); otherwise, proceeding to a step (S6-7).

(S6-7) Inputting logic signals V_(WL0c˜(n−1)c)=0, V_(WLnc)=1,V_(BL0c˜nc)=a_(n−1) and V_(SL0c˜nc)=b_(n−1) to calculatec_(n)=a_(n−1)·b_(n−1)+a_(n−1)·c_(n−1)+c_(n−1)·b_(n−1) and store c_(n) inR_(nc) of the 1T1R array H₁; inputting logic signals V_(WL0˜(n−3))=0,V_(WL(n−2)˜(n−1))=1, V_(BL0˜(n−3))=0, V_(BL(n−2))=b_(n−2),V_(BL(n−1))=a_(n−1), V_(SL0˜(n−3))=0, V_(SL(n−2))=c_(n−1) andV_(SL(n−1))=b_(n−1) to calculate s_(n−2)=a_(n−2)⊕b_(n−2)⊕c_(n−2) ands_(n−1)=c_(n−1)·a_(n−1)+c_(n−1) ·a_(n−1)·b_(n−1) +c_(n−1)·a_(n−1)·b_(n−1) and store s_(n−2) in R_(n−2) of the 1T1R array H₂ and s_(n−1)in R_(n−1) of the 1T1R array H₂.

(S6-8) Inputting logic signals V_(WL0˜(n−2))=0, V_(WL(n−1))=1,V_(BL0˜(n−2))=0, V_(BL(n−1))=b_(n−1), V_(SL0˜(n−2))=0 andV_(SL(n−1))=c_(n) to calculate s_(n−1)=a_(n−1)⊕b_(n−1)⊕c_(n−1) and stores_(n−1) in R_(n−1) of the 1T1R array H₂.

In general, with the above technical solution conceived by the presentinvention, a computing array based on 1T1R device is provided, and basedon the computing array according to the present invention, multipleoperation circuits are provided, which can achieve the followingbeneficial effects.

(1) The operation circuits are based on the computing array based on1T1R device, and can directly store the calculated result in the 1T1Rdevices of the computing array while performing the logic operation,thereby achieving the fusion of computing and storage.

(2) The operation circuits according to the present invention cancomplete all logical operations in two steps when implementing 16 kindsof Boolean logic operations, greatly simplifying the design of the logiccircuit and reducing the complexity of the integration process.

(3) By setting a different number of 1T1R arrays in the computing arrayand a different number of 1T1R devices in the 1T1R array in combinationwith the corresponding operating methods, in addition to 16 basicBoolean logic operations, complex operations such as a 1-bit full adder,a multi-bit step-by-step carry adder and optimization design thereof, a2-bit data selector, a multi-bit carry select adder and a multi-bitpre-calculation adder can be realized.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of a computing array based on 1T1R deviceaccording to an embodiment of the present invention.

FIG. 2 is a schematic diagram of a 1T1R array in the computing arrayaccording to the embodiment of the present invention.

FIG. 3 is a schematic diagram of a three-dimensional structure and anequivalent circuit diagram of the 1T1R device according to theembodiment of the present invention, in which (a) is a schematic diagramof a three-dimensional structure of the 1T1R device; and (b) is anequivalent circuit diagram of a 1T1R device.

FIG. 4 is a block diagram and an equivalent circuit diagram of anoperation circuit of a 1-bit full adder based on the computing arrayaccording to an embodiment of the present invention, in which (a) is ablock diagram of the operation circuit of the 1-bit full adder; and (b)is an equivalent circuit diagram of the operation circuit of the 1-bitfull adder.

FIG. 5 is an equivalent circuit diagram of an operation circuit of an8-bit step-by-step carry adder based on the computing array according toan embodiment of the present invention.

FIG. 6 is an equivalent circuit diagram of an operation circuit of anoptimized 8-bit step-by-step carry adder based on the computing arrayaccording to an embodiment of the present invention.

FIG. 7 is a block diagram and an equivalent circuit diagram of anoperation circuit of a 2-bit data selector based on the computing arrayaccording to an embodiment of the present invention, in which (a) is ablock diagram of the operation circuit of the 2-bit data selector; and(b) is an equivalent circuit diagram of the operation circuit of the2-bit data selector.

FIG. 8 is an equivalent circuit diagram of an operation circuit of an8-bit carry select adder based on the computing array according to anembodiment of the present invention.

FIG. 9 is an equivalent circuit diagram of an operation circuit of an8-bit pre-calculation adder based on the computing array according to anembodiment of the present invention.

In all figures, the same elements or structures are denoted by the samereference numerals, in which:

100: source line decoder, 101: word line decoder, 102: bit line decoder,103: signal amplifier, 104: state controller, 105: control signal modem,106: data transmission circuit, 300: bit Line, 301: upper electrode ofRRAM, 302: functional layer of RRAM, 303: lower electrode of RRAM, 304:source line, 305: gate of transistor, 306: insulating layer oftransistor, 307: source of transistor, 308: drain of transistor, and309: substrate of transistor.

DETAILED DESCRIPTION OF THE EMBODIMENTS

For clear understanding of the objectives, features and advantages ofthe present invention, detailed description of the present inventionwill be given below in conjunction with accompanying drawings andspecific embodiments. It should be noted that the embodiments describedherein are only meant to explain the present invention, and not to limitthe scope of the present invention. Furthermore, the technical featuresrelated to the embodiments of the invention described below can bemutually combined if they are not found to be mutually exclusive.

A computing array based on 1T1R device according to the presentinvention, as shown in FIG. 1, includes: one or more 1T1R arrays and aperipheral circuit; the 1T1R array is configured to achieve operationand storage of an operation result, and the peripheral circuit isconfigured to transmit data and control signals to control operation andstorage processes of the 1T1R array.

The 1T1R array, as shown in FIG. 2, includes 1T1R devices arranged in anarray, word lines WL, bit lines BL and source lines SL; the 1T1R devicesrealize storage and processing of information through differentresistance states; the 1T1R devices in the same row are connected to thesame word line, and the 1T1R devices in the same column are connected tothe same bit line and source line; and through applying differentsignals to the word lines WL, bit lines BL and source lines SL,different operations are achieved and operation results are stored.

The 1T1R device, as shown in FIG. 3, includes a transistor and aresistive element. The transistor includes a substrate 309, a source307, a drain 308, an insulating layer 306 and a gate 305. In thisembodiment, the resistive element is a resistive random access memory(RRAM), which includes: an upper electrode 301, a functional layer 302and a lower electrode 303. The source 307 of the transistor is connectedto the source line 304, the gate 305 of the transistor is connected tothe word line, the upper electrode 301 of RRAM is connected to the bitline 300, and the lower electrode 303 of RRAM is connected to the drain308 of the transistor.

The resistance states of the 1T1R devices include: High Resistance H andLow Resistance L. The resistance state of the 1T1R device can bereversibly transformed under the stimulation of an applied signal,namely, with the stimulation of an applied signal, the resistance stateof the 1T1R device can be transformed from High Resistance to LowResistance, and with the stimulation of another applied signal, theresistance state of the 1T1R device can be transformed from LowResistance to High Resistance. By using the two resistance states of the1T1R device, storage and processing of information can be achieved.

As shown in FIG. 1, the peripheral circuit includes a state controller104, a word line decoder 101, a source line decoder 100, a bit linedecoder 102, a signal amplifier 103, a control signal modem 105 and adata transmission circuit 106, in which:

The state controller 104 has a data input/output terminal Data, anaddress input terminal Address, a clock signal input terminal CLK, aresult input terminal, a word line output terminal, a bit line outputterminal, a source line output terminal and a secondary output terminal;the data input/output terminal Data of the state controller isconfigured to input calculated data on the one hand and output acalculated result on the other hand, the address input terminal Addressof the state controller is configured to input address information of aselected device, the clock signal input terminal CLK of the statecontroller is configured to input a clock signal for controlling acalculation timing, and the result input terminal is configured to inputa calculated result generated by a pre-stage circuit; the statecontroller generates a control signal according to the input data,address information, clock signal and calculated result, or outputs afinal calculated result.

An input terminal of the word line decoder 101 is connected to the wordline output terminal of the state controller 104, an output terminal ofthe word line decoder 101 is connected to the word line of the 1T1Rarray; the word line decoder 101 decodes the control signal generated bythe state controller 104 to obtain a word line control signal, andinputs the word line control signal to the 1T1R devices through the wordline of the 1T1R array.

An input terminal of the bit line decoder 102 is connected to the bitline output terminal of the state controller 104, an output terminal ofthe bit line decoder 102 is connected to the bit line of the 1T1R array;the bit line decoder 102 decodes the control signal generated by thestate controller 104 to obtain a bit line control signal, and inputs thebit line control signal to the 1T1R devices through the bit line of the1T1R array.

An input terminal of the source line decoder 100 is connected to thesource line output terminal of the state controller 104, an outputterminal of the source line decoder 100 is connected to the source lineof the 1T1R array; the source line decoder 100 decodes the controlsignal generated by the state controller 104 to obtain a source linecontrol signal, and inputs the source line control signal to the 1T1Rdevices through the source line of the 1T1R array.

The word line control signal, the bit line control signal and the sourceline control signal are commonly applied to the 1T1R array to controlstates of the 1T1R devices in the 1T1R array.

An input terminal of the signal amplifier 103 is connected to the bitline of the 1T1R array; when data information stored in the 1T1R arrayis read, the signal amplifier 103 converts an acquired resistance signalstored by the 1T1R device into a voltage signal and then outputs it tothe control signal modem 105.

A first input terminal of the control signal modem 105 is connected tothe secondary output terminal of the state controller 104, a secondinput terminal of the control signal modem 105 is connected to an outputterminal of the signal amplifier 103; the control signal modem 105decodes the control signal generated by the state controller 104 toobtain a control signal of a next-stage circuit, or directly transmitsthe data voltage signal output by the signal amplifier 103; thenext-stage circuit is the next 1T1R device in the same 1T1R array, or anext 1T1R array in the compute array.

An input terminal of the data transmission circuit 106 is connected toan output terminal of the control signal modem 105; the datatransmission circuit 106 feeds back the data voltage signal output bythe control signal modem 105 to the state controller 104 through theresult input terminal of the state controller 104, or transmits thecontrol signal output from the control signal modem 105 to a word linedecoder, a bit line decoder and a source line decoder of the next-stagecircuit.

The data input/output terminal Data, the address input terminal Addressand the clock signal input terminal CLK of the state controller 104respectively serve as a data input/output terminal, an address inputterminal and a clock signal input terminal of the computing array.

In the computing array based on 1T1R device, applied voltage pulses areused as input signals to perform logic operation, and the result of thelogic operation is characterized by the final resistance state of the1T1R device; the result of the logic operation can be non-volatilelystored in the resistance state of the device, the resistance state canbe read by a read signal of a small current (generally at the nanoamperelevel) or a small voltage (generally 0.2V or less), and the resistancesignal can be erased by applying a voltage pulse with a certainamplitude and pulse width.

In the computing array based on 1T1R device, Boolean logic operationsare achieved in the 1T1R devices by applying different voltage pulsesignals to the word lines, source lines and bit lines of the 1T1R array.The initial resistance state of the 1T1R device is defined as a logicsignal I, in which I=0 when the initial resistance state of the 1T1Rdevice is High Resistance, and I=1 when the initial resistance state ofthe 1T1R device is Low Resistance; the word line level voltage isdefined as a logic signal V_(WL), in which V_(WL)=0 when a zero-levelpulse is applied to the word line, and V_(WL)=1 when a forward voltagepulse is applied to the word line; the bit line level voltage is definedas a logic signal V_(BL), in which V_(BL)=0 when a zero-level pulse isapplied to the bit line, and V_(BL)=1 when a forward voltage pulse isapplied to the bit line; the source line level voltage is defined as alogic signal V_(SL), in which V_(SL)=0 when a zero-level pulse isapplied to the source line, and V_(SL)=1 when a forward voltage pulse isapplied to the source line; the result of the logical operation in the1T1R device is non-volatilely stored in the 1T1R device, and wheninformation stored in the 1T1R device is read, the resistance state ofthe 1T1R device is defined as a logic signal R, in which R=0 when theresistance state of the 1T1R device is High Resistance, and R=1 when theresistance state of the 1T1R device is Low Resistance; and a logicalrelationship between the logic signal I, the logic signal V_(WL), thelogic signal V_(BL), the logic signal V_(SL), and the logic signal R is:R=I· V _(WL) +I·V _(WL) ·V _(BL) +I·V _(WL)· V _(BL) · V _(SL) +Ī·V_(WL) ·V _(BL)· V _(ST)

In the computing array based on 1T1R device, Boolean logic operation areimplemented in a single 1T1R device, and specifically, the operatingmethod includes the following steps.

(1) Initializing the 1T1R device to obtain a logic signal I.

(2) Respectively applying a voltage pulse signal to a word line, asource line and a bit line to obtain a logic signal V_(WL), a logicsignal V_(SL) and a logic signal V_(BL).

(3) Reading a result of the logical operation, that is, a logic signalR.

By controlling values of the logic signals I, V_(WL), V_(BL) and V_(SL),the following 16 Boolean logic operations can be implemented:

implementation of logic 0: I=0, V_(WL)=0, V_(BL)=p and V_(SL)=q;

implementation of logic 1: I=1, V_(WL)=0, V_(BL)=p and V_(SL)=q;

implementation of p logic: I=p, V_(WL)=0, V_(BL)=0 and V_(SL)=q;

implementation of p logic: I=q, V_(WL)=0, V_(BL)=0 and V_(SL)=p;

implementation of p logic: I=p, V_(WL)=0, V_(BL)=p and V_(SL)=q;

implementation of q logic: I=q, V_(WL)=0, V_(BL)=p and V_(SL)=q;

implementation of p+q logic: I=p, V_(WL)=1, V_(BL)=p and V_(SL)=0;

implementation of p+q logic: I=1, V_(WL)=p, V_(BL)=0 and V_(SL)=q;

implementation of p·q logic: I=0, V_(WL)=p, V_(BL)=q and V_(SL)=0;

implementation of p·q logic: I=q, V_(WL)=p, V_(BL)=q and V_(SL)=1;

implementation of p+q logic: I=1, V_(WL)=1, V_(BL)=p and V_(SL)=q;

implementation of p+q logic: I=1, V_(WL)=p, V_(BL)=q and V_(SL)=1;

implementation of p·q logic: I=q, V_(WL)=1, V_(BL)=0 and V_(SL)=p;

implementation of p·q logic: I=p, V_(WL)=1, V_(BL)=0 and V_(SL)=q;

implementation of p·q+p·q logic: I=p, V_(WL)=q, V_(BL)=p and V_(SL)=p;and

implementation of p·q+p·q logic: I=q, V_(WL)=p, V_(BL)=q and V_(SL)=q.

Further, by inputting a logic signal V_(WL)=1 via the word line, a logicsignal V_(BL)=V_(read) via the bit line and a logic signal V_(SL)=0 viathe source line, the logic signal stored on the 1T1R device can be read,in which V_(read) is a voltage pulse signal applied when the resistancestate of the 1T1R device is read.

In the present invention, symbols similar to I, V_(WL), V_(BL) andV_(SL) are used to denote logical signals with the same concept, andsignals corresponding to different 1T1R devices are distinguished onlyby different subscripts.

FIG. 4 shows an operation circuit based on the computing array accordingto the present invention for implementing a 1-bit full adder, in which asum s₀ and a high-order carry c₁ are calculated according to a logicsignal a, a logic signal b and a low-order carry c₀ that are input; theoperation circuit includes: a 1T1R array A₁, a 1T1R array A₂ and a 1T1Rarray A₃; the 1T1R array A₁ includes a 1T1R device R_(b) for calculatingand storing intermediate data s₀*, a word line signal corresponding toR_(b) is V_(WLb), a bit line signal corresponding to R_(b) is V_(BLb)and a source line signal corresponding to R_(b) is V_(SLb); the 1T1Rarray A₂ includes a 1T1R device R_(c) for calculating and storing thehigh-order carry c₁, a word line signal corresponding to R_(c) isV_(WLc), a bit line signal corresponding to R_(c) is V_(BLc) and asource line signal corresponding to R_(c) is V_(SLc); the 1T1R array A₃includes a 1T1R device R_(s) for calculating and storing the sum s₀, aword line signal corresponding to R_(s) is V_(WLs), a bit line signalcorresponding to R_(s) is V_(BLs) and a source line signal correspondingto R_(s) is V_(SLs); and the intermediate data s₀* calculated by the1T1R array A₁ and the high-order carry c₁ calculated by the 1T1R arrayA₂ are converted by the signal amplifier and the control signal modem,and then transmitted to the 1T1R array A₃ through the data transmissioncircuit.

In conjunction with the operation circuit based on the computing arrayshown in FIG. 4, an operating method according to the present inventioncomprises the following steps.

(S1-1) Inputting logic signals V_(WLc)=1, V_(BLc)=c₀ and V_(SLc)=c₀ towrite the input logic signal c₀ into R_(c) of the 1T1R array A₂;inputting logic signals V_(WLb)=1, V_(BLb)=a₀ and V_(SLb)=a₀ , to writethe input logic signal a₀ into R_(b) of the 1T1R array A₁; inputtinglogic signals V_(WLs)=1, V_(BLs)=a₀ and V_(SLs)=a₀ to write the inputlogic signal a₀ into R_(s) of the 1T1R array A₃.

(S1-2) Inputting logic signals V_(WLc)=1, V_(BLc)=a₀ and V_(SLc)=b₀ tocalculate a high-order carry c₁=a₀·b₀+a₀·c₀+c₀·b₀ and store c₁ in R_(c)of the 1T1R array A₂; inputting logic signals V_(WLb)=b₀, V_(BLb)=a₀ andV_(SLb)=a₀ to calculate an intermediate result s₀*=a₀⊕b₀ and store s₀*in R_(b) of the 1T1R array A₁; inputting logic signals V_(WLs)=b₀,V_(BLs)=a₀ and V_(SLs)=a₀ to calculate an intermediate result s₀* andstore s₀* in R_(s) of the 1T1R array A₃.

(S1-3) reading the logic signal c₁ stored in R_(c) of the 1T1R array A₂;reading the logic signal s₀* stored in R_(b) of the 1T1R array A₁;inputting logic signals V_(WLs)=c₀, V_(BLs)=s₀* and V_(SLs)=s₀* tocalculate a sum s₀=a₀⊕b₀⊕c₀ and store s₀ in R_(s) of the 1T1R array A₃.

(S1-4) reading the logic signal s₀ stored in R_(s) of the 1T1R array A₃.

FIG. 5 shows an operation circuit based on the computing array accordingto the present invention for implementing an 8-bit step-by-step carryadder, in which sums s_(0˜7) and carry information c₈ are calculatedaccording to input data a_(0˜7) and b_(0˜7) and carry information c₀;the operation circuit includes: a 1T1R array D₁, a 1T1R array D₂ and a1T1R array D₃; the 1T1R array D₁ includes eight 1T1R devicesR_(0b)˜R_(7b) for calculating and storing intermediate results, wordline control signals corresponding to R_(0b)˜R_(7b) are respectivelyV_(WL0b)˜V_(WL7b), bit line control signals corresponding toR_(0b)˜R_(7b) are respectively V_(BL0b)˜V_(BL7b), and source linecontrol signals corresponding to R_(0b)˜R_(7b) are respectivelyV_(SL0b)˜V_(SL7b); the 1T1R array D₁ is used for data backup; the 1T1Rarray D₂ includes a 1T1R device R₈ for calculating and storing carrydata c_(i) (i is an integer from 0 to 8), a word line control signalcorresponding to R₈ is V_(WL8), a bit line control signal correspondingto R₈ is V_(BL8) and a source line control signal corresponding to R₈ isV_(SL8); the 1T1R array D₃ includes eight 1T1R devices R₀˜R₇ forcalculating and storing addition operation results s_(0˜7), word linecontrol signals corresponding to R₀˜R₇ are respectively V_(WL0)˜V_(WL7),bit line control signals corresponding to R₀˜R₇ are respectivelyV_(BL0)˜V_(BL7), and source line control signals corresponding to R₀˜R₇are respectively V_(SL0)˜V_(SL7); and the intermediate data s_(0˜7)*calculated by the 1T1R array D₁ and the carry information c₁ calculatedby the 1T1R array D₂ are converted by the signal amplifier and thecontrol signal modem, and then transmitted to the 1T1R array D₃ throughthe data transmission circuit.

In conjunction with the operation circuit based on the computing arrayshown in FIG. 5, an operating method according to the present inventioncomprises the following steps.

(S2-1) Inputting logic signals V_(WL0˜7)=1, V_(BL0˜7)=a_(0˜7) andV_(SL0˜7)=a_(0˜7) to write the input data a_(0˜7) into R₀˜R₇ of the 1T1Rarray D₃; inputting logic signals V_(WL8)=1, V_(BL8)=c₀ and V_(SL8)=c₀to write the lower-order carry c₀ into R₈ of the 1T1R array D₂.

(S2-2) inputting logic signals V_(WL0˜7)=b_(0˜7), V_(BL0˜7)=a_(0˜7) andV_(SL0˜7)=a_(0˜7) to calculate intermediate resultss_(0˜7)*=a_(0˜7)⊕b_(0˜7) and store s_(0˜7)* in R₀˜R₇ of the 1T1R arrayD₃; inputting logic signals V_(WL0b˜7b)=b_(0˜7), V_(BL0b˜7b)=a_(0˜7) andV_(SL0b˜7b)=a_(0˜7) to calculate intermediate results s_(0˜7)* and stores_(0˜7)* in R_(0b)˜R_(7b) of the 1T1R array D₁; inputting logic signalsV_(WL8)=1, V_(BL8)=a₀ and V_(SL8)=b₀ to calculate c₁=a₀·b₀+a₀·c₀+c₀·b₀and store c₁ in R₈ of the 1T1R array D₂.

(S2-3) Reading s₀* from R_(0b) of the 1T1R array D₁, and reading s₁*from R_(1b) of the 1T1R array D1; inputting logic signals V_(WL0)=c₀,V_(WL1)=c₁, V_(WL2˜7)=0, V_(BL0)=s₀*, V_(BL1)=s₁*, V_(BL2˜7)=0,V_(SL0)=s₀*, V_(SL1)=s₁* and V_(SL2˜7)=0 to calculate s₀=a₀⊕b₀⊕c₀ ands₁=a₁⊕b₁⊕c₁, and store s₀ in R₀ of the 1T1R array D₃ and s₁ in R₁ of the1T1R array D₃.

(S2-4) Inputting logic signals V_(WL8)=1, V_(BL8)=a₁ and V_(SL8)=b₁ tocalculate c₂=a₁·b₁+a₁·c₁+c₁·b₁ and store c₂ in R₈ of the 1T1R array D₂.

(S2-5) Reading s₂* from R_(2b) of the 1T1R array D₁; inputting logicsignals V_(WL0˜1)=0, V_(WL2)=c₂, V_(WL3˜7)=0, V_(BL0˜1)=0, V_(BL2)=s₂*,V_(BL3˜7)=0, V_(SL0˜1)=0, V_(SL2)=s₂* and V_(SL3˜7)=0 to calculates₂=a₂⊕b₂⊕c₂ and store s₂ in R₂ of the 1T1R array D₃.

(S2-6) Inputting logic signals V_(WL8)=1, V_(BL8)=a₂ and V_(SL8)=b₂ tocalculate c₃=a₂·b₂+a₂·c₂+c₂·b₂ and store c₃ in R₈ of the 1T1R array D₂.

(S2-7) Reading s₃* from R_(3b) of the 1T1R array D₁; inputting logicsignals V_(WL0˜2)=0, V_(WL3)=c₃, V_(WL4˜7)=0, V_(BL0˜2)=0, V_(BL3)=s₃*,V_(BL4˜7)=0, V_(SL0˜2)=0, V_(SL3)=s₃* and V_(SL4˜7)=0 to calculates₃=a₃⊕b₃⊕c₃ and store s₃ in R₃ of the 1T1R array D₃.

(S2-8) inputting logic signals V_(WL8)=1, V_(BL8)=a₃ and V_(SL8)=b₃ tocalculate c₄=a₃·b₃+a₃·c₃+c₃·b₃ and store c₄ in R₈ of the 1T1R array D₂.

(S2-9) Reading s₄* from R_(4b) of the 1T1R array D₁; inputting logicsignals V_(WL0˜3)=0, V_(WL4)=c₄, V_(WL5˜7)=0, V_(BL0˜3)=0, V_(BL4)=s₄*,V_(BL5˜7)=0, V_(SL0˜3)=0, V_(SL4)=s₄* and V_(SL5˜7)=0 to calculates₄=a₄⊕b₄⊕c₄ and store s₄ in R₄ of the 1T1R array D₃.

(S2-10) Inputting logic signals V_(WL8)=1, V_(BL8)=a₄ and V_(SL8)=b₄ tocalculate c₅=a₄·b₄+a₄·c₄+c₄·b₄ and store c₅ in R₈ of the 1T1R array D₂.

(S2-11) Reading s₅* from R_(5b) of the 1T1R array D₁; inputting logicsignals V_(WL0˜4)=0, V_(WL5)=c₅, V_(WL6˜7)=0, V_(BL0˜4)=0, V_(BL5)˜s₅*,V_(BL6˜7)=0, V_(SL0˜4)=0, V_(SL5)=s₅* and V_(SL6˜7)=0 to calculates₅=a₅⊕b₅⊕c₅ and store s₅ in R₅ of the 1T1R array D₃.

(S2-12) Inputting logic signals V_(WL8)=1, V_(BL8)=a₅ and V_(SL8)=b₅ tocalculate c₆=a₅·b₅+a₅·c₅+c₅·b₅ and store c₆ in R₈ of the 1T1R array D₂.

(S2-13) Reading s₆* from R_(6b) of the 1T1R array D₁; inputting logicsignals V_(WL0˜5)=0, V_(WL6)=c₆, V_(WL7)=0, V_(BL0˜5)=0, V_(BL6)=s₆*,V_(BL7)=0, V_(SL0˜5)=0, V_(SL6)=s₆* and V_(SL7)=0 to calculates₆=a₆⊕b₆⊕c₆ and store s₆ in R₆ of the 1T1R array D₃.

(S2-14) Inputting logic signals V_(WL8)=1, V_(BL8)=a₆ and V_(SL8)=b₆ tocalculate c₇=a₆·b₆+a₆·c₆+c₆·b₆ and store c₇ in R₈ of the 1T1R array D₂.

(S2-15) Reading s₇* from R_(7b) of the 1T1R array D₁; inputting logicsignals V_(WL0˜6)=0, V_(WL7)=c₇, V_(BL0˜6)=0, V_(BL7)=s₇*, V_(SL0˜6)=0and V_(SL7)=s₇* to calculate s₇=a₇⊕b₇⊕c₇ and store s₇ in R₇ of the 1T1Rarray D₃.

(S2-16) Inputting logic signals V_(WL8)=1, V_(BL8)=a₇ and V_(SL8)=b₇ tocalculate c₈=a₇·b₇+a₇·c₇+c₇·b₇ and store c₈ in R₈ of the 1T1R array D₂.

FIG. 6 shows an operation circuit based on the computing array accordingto the present invention for implementing an optimized 8-bitstep-by-step carry adder, in which sums s_(0˜7) and carry information c₈are calculated according to input data a_(0˜7) and b_(0˜7) and carryinformation c₀; the operation circuit includes: a 1T1R array E₁, a 1T1Rarray E₂ and a 1T1R array E₃; the 1T1R array E₁ includes eight 1T1Rdevices R_(0b)˜R_(7b) for calculating and storing data s_(0˜7)*, wordline control signals corresponding to R_(0b)˜R_(7b) are respectivelyV_(WL0b)˜V_(WL7b), bit line control signals corresponding toR_(0b)˜R_(7b) are respectively V_(BL0b)˜V_(BL7b), and source linecontrol signals corresponding to R_(0b)˜R_(7b) are respectivelyV_(SL0b)˜V_(SL7b); the 1T1R array E₁ is used for data backup; the 1T1Rarray E₂ includes nine 1T1R devices R_(0c)˜R_(8c) for calculating andstoring carry data c_(i) (i is an integer from 0 to 8), word linecontrol signals corresponding to R_(0c)˜R_(8c) are respectivelyV_(WL0c)˜V_(WL8c), bit line control signals corresponding toR_(0c)˜R_(8c) are respectively V_(BL0c)˜V_(BL8c), and source linecontrol signals corresponding to R_(0c)˜R_(8c) are respectivelyV_(SL0c)˜V_(SL8c); the 1T1R array E₃ includes eight 1T1R devices R₀˜R₇for calculating and storing addition operation results s_(0˜7); and theintermediate data s_(0˜7)* calculated by the 1T1R array E₁ and the carryinformation c_(i) calculated by the 1T1R array E₂ are converted by thesignal amplifier and the control signal modem, and then transmitted tothe 1T1R array E₃ through the data transmission circuit.

In conjunction with the operation circuit based on the computing arrayshown in FIG. 6, an operating method according to the present inventioncomprises the following steps.

(S3-1) inputting logic signals V_(WL0˜7)=1, V_(BL0˜7)=a_(0˜7) andV_(SL0˜7)=a_(0˜7) to write the input operational data a_(0˜7) into R₀˜R₇of the 1T1R array E₃; inputting logic signals V_(WL0b˜7b)=1,V_(BL0b˜7b)=a_(0˜7) and V_(SL0b˜7b)=a_(0˜7) to write the inputoperational data a_(0˜7) into R_(0b)˜R_(7b) of the 1T1R array E₁;inputting logic signals V_(WL0c˜8c)=1, V_(BL0c˜8)=c₀ and V_(SL0c˜8c)=c₀to write the carry information c₀ into R_(0c)˜R_(8c) of the 1T1R arrayE₂.

(S3-2) Inputting logic signals V_(WL0˜7)=b_(0˜7), V_(BL0˜7)=a_(0˜7) andV_(SL0˜7)=a_(0˜7) to calculate intermediate resultss_(0˜7)*=a_(0˜7)⊕b_(0˜7) and store s_(0˜7)* in R₀˜R₇ of the 1T1R arrayE₃; inputting logic signals V_(WL0b˜7b)=b_(0˜7), V_(BL0b˜7b)=a_(0˜7) andV_(SL0b˜7b)=a_(0˜7) to calculate intermediate results s_(0˜7)* and stores_(0˜7)* in R_(0b)˜R_(7b) of the 1T1R array E₁; inputting logic signalsV_(WL0c)=0, V_(WL1c˜8c)=1, V_(BL0c˜8c)=a₀ and V_(SL0c˜8c)=b₀ tocalculate c₁=a₀·b₀+a₀·c₀+c₀·b₀ and store c₁ in R_(1c˜8c) of the 1T1Rarray E₂.

(S3-3) Reading s₀* from R_(0b) of the 1T1R array E₁, and reading s₁*from R_(1b) of the 1T1R array E1; inputting logic signals V_(WL0)=c₀,V_(WL1)=c₁, V_(WL2˜7)=0, V_(BL0)=s₀*, V_(BL1)=s₁*, V_(BL2˜7)=0,V_(SL0)=s₀*, V_(SL1)=s₁* and V_(SL2˜7)=0 to calculate s₀=a₀⊕b₀⊕c₀ ands₁=a₁⊕b₁⊕c₁, and store so in R₀ of the 1T1R array E₃ and s₁ in R₁ of the1T1R array E₃; inputting logic signals V_(WL0c˜1c)=0, V_(WL2c˜8c)=1,V_(BL0c˜8c)=a₁ and V_(SL0c˜8c)=b₁ to calculate c₂=a₁·b₁+a₁·c₁+c₁·b₁ andstore c₂ in R_(2c˜8c) of the 1T1R array E₂.

(S3-4) Reading s₂* from R_(2b) of the 1T1R array E₁; inputting logicsignals V_(WL0˜1)=0, V_(WL2)=c₂, V_(WL3˜7)=0, V_(BL0˜1)=0, V_(BL2)=s₂*,V_(BL3˜7)=0, V_(SL0˜1)=0, V_(SL2)=s₂* and V_(SL3˜7)=0 to calculates₂=a₂⊕b₂⊕c₂, and store s₂ in R₂ of the 1T1R array E₃; inputting logicsignals V_(WL0˜2c)=0, V_(WL3c˜8c)=1, V_(BL0c˜8c)=a₂ and V_(SL0c˜8c)=b₂to calculate c₃=a₂·b₂+a₂·c₂+c₂·b₂ and store c₃ in R_(3c˜8c) of the 1T1Rarray E₂.

(3-5) Reading s₃* from R_(3b) of the 1T1R array E₁; inputting logicsignals V_(WL0˜2)=0, V_(WL3)=c₃, V_(WL4˜7)=0, V_(BL0˜2)=0, V_(BL3)=s₃*,V_(BL4˜7)=0, V_(SL0˜2)=0, V_(SL3)=s₃* and V_(SL4˜7)=0 to calculates₃=a₃⊕b₃⊕c₃ and store s₃ in R₃ of the 1T1R array D₃; inputting logicsignals V_(WL0c˜3c)=0, V_(WL4c˜8c)=1, V_(BL0c˜8c)=a₃ and V_(SL0c˜8c)=b₃to calculate c₄=a₃·b₃+a₃·c₃+c₃·b₃ and store c₄ in R_(4c˜8c) of the 1T1Rarray E₂.

(3-6) Reading s₄* from R_(4b) of the 1T1R array E₁; inputting logicsignals V_(WL0˜3)=0, V_(WL4)=c₄, V_(WL5˜7)=0, V_(BL0˜3)=0, V_(BL4)=s₄*,V_(BL5˜7)=0, V_(SL0˜3)=0, V_(SL4)=s₄* and V_(SL5˜7)=0 to calculates₄=a₄⊕b₄⊕c₄ and store s₄ in R₄ of the 1T1R array E₃; inputting logicsignals V_(WL0c˜4c)=0, V_(WL5c˜8c)=1, V_(BL0c˜8c)=a₄ and V_(SL0c˜8c)=b₄to calculate c₅=a₄·b₄+a₄·c₄+c₄·b₄ and store c₅ in R_(5c˜8c) of the 1T1Rarray E₂.

(3-7) Reading s₅* from R_(5b) of the 1T1R array E₁; inputting logicsignals V_(WL0˜4)=0, V_(WL5)=c₅, V_(WL6˜7)=0, V_(BL0˜4)=0, V_(BL5)˜s₅*,V_(BL6˜7)=0, V_(SL0˜4)=0, V_(SL5)=s₅* and V_(SL6˜7)=0 to calculates₅=a₅⊕b₅⊕c₅ and store s₅ in R₅ of the 1T1R array E₃; inputting logicsignals V_(WL0˜5c)=1, V_(WL6c˜8c)=1, V_(BL0c˜8c)=a₅ and V_(SL0c˜8c)=b₅to calculate c₆=a₅·b₅+a₅·c₅+c₅·b₅ and store c₆ in R_(6c˜8c) of the 1T1Rarray E₂.

(3-8) Reading s₆* from R_(6b) of the 1T1R array E₁; inputting logicsignals V_(WL0˜5)=0, V_(WL6)=c₆, V_(WL7)=0, V_(BL0˜5)=0, V_(BL6)=s₆*,V_(BL7)=0, V_(SL0˜5)=0, V_(SL6)=s₆* and V_(SL7)=0 to calculates₆=a₆⊕b₆⊕c₆ and store s₆ in R₆ of the 1T1R array E₃; inputting logicsignals V_(WL7c˜8c)=1, V_(BL0c˜8c)=a₆ and V_(SL0c˜8c)=b₆ to calculatec₇=a₆·b₆+a₆·c₆+c₆·b₆ and store c₇ in R_(7c˜8c) of the 1T1R array E₂.

(3-9) Reading s₇* from R_(7b) of the 1T1R array E1; inputting logicsignals V_(WL0˜6)=0, V_(WL7)=c₇, V_(BL0˜6)=0, V_(BL7)=s₇*, s_(L0˜6)=0and V_(SL7)=s₇* to calculate s₇=a₇⊕b₇⊕c₇ and store s₇ in R₇ of the 1T1Rarray E₃; and inputting logic signals V_(WL0c˜7c)=0, V_(WL8c)=1,V_(BL0c˜8c)=a₇ and V_(SL0c˜8c) b₇ to calculate c₈=a₇·b₇+a₇·c₇+c₇·b₇ andstore c₈ in R_(8c) of the 1T1R array E₂.

FIG. 7 shows an operation circuit based on the computing array accordingto the present invention for implementing a 2-bit data selector, inwhich a logic signal a, a logic signal b and a control signal Sel areinput to output the logic signal a or the logic signal b by controllinga value of the control signal Sel; and the operation circuit includes a1T1R array F, and the 1T1R array F includes one 1T1R device R.

In conjunction with the operation circuit based on the computing arrayshown in FIG. 7, an operating method according to the present inventioncomprises the following steps.

(S4-1) Inputting logic signals V_(WL)=1, V_(BL)=a and V_(SL)=ā toinitialize the 1T1R device R, and write the input logic signal a into Rof the 1T1R array F.

(S4-2) inputting logic signals V_(WL)=Sel, V_(BL)=b and V_(SL)=b toinput the logic signal b and the control signal Sel so as to select anoutput logic signal out,

wherein the logic signal a and the logic signal b represent only twoindependent logic signals; when the control signal Sel=0, the outputsignal out=a; and when the control signal Sel=1, the output signalout=b.

FIG. 8 shows an operation circuit based on the computing array accordingto the present invention for implementing an 8-bit carry select adder,in which sums s_(0˜7) and carry information c₈ are calculated accordingto input data a_(0˜7) and b_(0˜7) and carry information c₀, and in thecalculation process, according to the carry information of each bit, anXNOR operation result or an XOR operation result of the correspondingbit of the operation data is selected as bit information of the sum; theoperation circuit includes a 1T1R array G₁, a 1T1R array G₂ and a 1T1Rarray G₃; the 1T1R array G₁ includes eight 1T1R devices R_(0x)˜R_(7x)for calculating and storing XNOR operation results of data a_(0˜7) andb_(0˜7) (X_(0˜7)=a_(0˜7) XNOR b_(0˜7)), word line control signalscorresponding to R_(0x)˜R_(7x) are respectively V_(WL0x)˜V_(WL7x), bitline control signals corresponding to R_(0x)˜R_(7x) are respectivelyV_(BL0x)˜V_(BL7x), and source line control signals corresponding toR_(0x)˜R_(7x) are respectively V_(SL0x)˜V_(SL7x); the 1T1R array G₂includes nine 1T1R devices R_(0c)˜R_(8c) for calculating carry datac_(i) (i is an integer from 0 to 8), word line control signalscorresponding to R_(0c)˜R_(8c) are respectively V_(WL0c)˜V_(WL8c), bitline control signals corresponding to R_(0c)˜R_(8c) are respectivelyV_(BL0c)˜V_(BL8c), and source line control signals corresponding toR_(0c)˜R_(8c) are respectively V_(SL0c)˜V_(SL8c); the 1T1R array G₃includes eight 1T1R devices R₀˜R₇ for calculating and storing additionoperation results s_(0˜7), word line control signals corresponding toR₀˜R₇ are respectively V_(WL0)˜V_(WL7), bit line control signalscorresponding to R₀˜R₇ are respectively V_(BL0)˜V_(BL7), and source linecontrol signals corresponding to R₀˜R₇ are respectively V_(SL0)˜V_(SL7);and the XNOR operation results X_(0˜7) calculated by the 1T1R array G₁and the carry information c_(i) calculated by the 1T1R array G₂ areconverted by the signal amplifier and the control signal modem, and thentransmitted to the 1T1R array G₃ through the data transmission circuit.

In conjunction with the operation circuit based on the computing arrayshown in FIG. 8, an operating method according to the present inventioncomprises the following steps.

(S5-1) Inputting logic signals V_(WL0x˜7x)=1, V_(BL0x˜7x)=b_(0˜7) andV_(SL0x˜7x)=b_(0˜7) to store the result b_(0˜7) of inverting the inputoperation data b_(0˜7) in R_(0x)˜R_(7x) of the 1T1R array G1; inputtinglogic signals V_(WL0c˜8c)=1, V_(BL0c˜8c)=c₀ and V_(SL0c˜8c)=c₀ to storec₀ in R_(0c)˜R_(8c) of the 1T1R array G₂; inputting logic signalsV_(WL0˜7)=1, V_(BL0˜7)=a₀₋₇ and V_(SL0˜7)=a_(0˜7) to store the inputoperational data a_(0˜7) in R₀˜R₇ of the 1T1R array G₃.

(S5-2) Inputting logic signals V_(WL0x˜7x)=a_(0˜7), V_(BL0x˜7x)=b₀₋₇ andV_(SL0x˜7x)=b_(0˜7) to calculate XNOR operation results X_(0˜7)=a_(0˜7)XNOR b_(0˜7) of the calculated data a_(0˜7) and b_(0˜7) and storeX_(0˜7) in R_(0x)˜R_(7x) of the 1T1R array G₁; inputting logic signalsV_(WL0c=)0, V_(WL1c˜8c)=1, V_(BL0c˜8c)=a₀ and V_(SL0c˜8c)=b₀ tocalculate c₁=a₀·b₀+a₀·c₀+c₀·b₀ and store c₁ in R_(1c˜8c) of the 1T1Rarray G₂; inputting logic signals V_(WL0˜7)=b₀₋₇, V_(BL0˜7)=a_(0˜7) andV_(SL0˜7)=a_(0˜7) to calculate XOR operation resultss_(0˜7)*=a_(0˜7)⊕b_(0˜7) and store s₀₋₇* in R₀˜R₇ of the 1T1R array G₃.

(S5-3) Inputting logic signals V_(WL0c˜1c)=0, V_(WL2c˜8c)=1,V_(BL0c˜8c)=a₁ and V_(SL0c˜8c)=b₁ to calculate c₂=a₁·b₁+a₁·c₁+c₁·b₁ andstore c₂ in R_(2c˜8c) of the 1T1R array G₂; inputting logic signalsV_(WL0)=c₀, V_(WL1)=c₁, V_(WL2˜7)=0, V_(BL0˜7)=X_(0˜7) andV_(SL0˜7)=X_(0˜7) to calculate s₀ and s₁ and store s₀ in R₀ of the 1T1Rarray G₃ and s₁ in R₁ of the 1T1R array G₃; when c₀=0, s₀=a₀⊕b₀, andwhen c₁=0, s₀=a₀⊕b₀ ; when c₁=0, s₁=a₁⊕b₁, and when c₁=1, s₁=a₁⊕b₁ .

(S5-4) Inputting logic signals V_(WL0c˜2c)=0, V_(WL3c˜8c)=1,V_(BL0c˜8c)=a₂ and V_(SL0c˜8c)=b₂ to calculate c₃=a₂·b₂+a₂·c₂+c₂·b₂ andstore c₃ in R_(3c˜8c) of the 1T1R array G₂; inputting logic signalsV_(WL0˜1)=0, V_(WL2)=c₂, V_(WL3˜7)=0, V_(BL0˜7)=X_(0˜7) andV_(SL0˜7)=X_(0˜7) to calculate s₂ and store s₂ in R₂ of the 1T1R arrayG₃; when c₂=0, s₂=a₂⊕b₂, and when c₂=1, s₂=s₂=a₂⊕b₂ .

(S5-5) Inputting logic signals V_(WL0c˜3c)=0, V_(WL4c˜8c)=1,V_(BL0c˜8c)=a₃ and V_(SL0c˜8c)=b₃ to calculate c₄=a₃·b₃+a₃·c₃+c₃·b₃ andstore c₄ in R_(4c˜8c) of the 1T1R array G₂; inputting logic signalsV_(WL0˜2)=0, V_(WL3)=c₃, V_(WL4˜7)=0, V_(BL0˜7)=X_(0˜7) andV_(SL0˜7)=X_(0˜7) to calculate s₃ and store s₃ in R₃ of the 1T1R arrayG₃; when c₃=0, s₃=a₃⊕b₃, and when c₃=1, s₃=a₃⊕b₃ .

(S5-6) Inputting logic signals V_(WL0c˜4c)=0, V_(WL5c˜8c)=1,V_(BL0c˜8c)=a₄ and V_(SL0c˜8c)=b₄ to calculate c₅=a₄·b₄+a₄·c₄+c₄·b₄ andstore c₅ in R_(5c-8c) of the 1T1R array G₂; inputting logic signalsV_(WL0˜3)=0, V_(WL4)=c₄, V_(WL5˜7)=0, V_(BL0˜7)=X_(0˜7) andV_(SL0˜7)=X_(0˜7) to calculate s₄ and store s₄ in R₄ of the 1T1R arrayG₃; when c₄=0, s₄=a₄⊕b₄, and when c₄=1, s₄=a₄⊕b₄ .

(S5-7) Inputting logic signals V_(WL0c˜5c)=0, V_(WL6c˜8c)=1,V_(BL0c˜8c)=a₅ and V_(SL0c˜8c)==b₅ to calculate c₆=a₅·b₅+a₅·c₅+c₅·b₅ andstore c₆ in R_(6c˜8c) of the 1T1R array G₂; inputting logic signalsV_(WL0˜4)=0, V_(WL5)=c₅, V_(WL6˜7)=0, V_(BL0˜7)=X_(0˜7) andV_(SL0˜7)=X_(0˜7) to calculate s₅ and store s₅ in R₅ of the 1T1R arrayG₃; when c₅=0, s₅=a₅⊕b₅, and when c₅=1, s₅=a₅⊕b₅ .

(S5-8) Inputting logic signals V_(WL0c˜6c)=0, V_(WL7c˜8c)=1,V_(BL0c˜8c)=a₆ and V_(SL0c˜8c)==b₆ to calculate c₇=a₆·b₆+a₆·c₆+c₆·b₆ andstore c₇ in R_(7c˜8c) of the 1T1R array G₂; inputting logic signalsV_(WL0˜5)=0, V_(WL6)=c₆, V_(WL7)=0, V_(BL0˜7)=X_(0˜7) andV_(SL0˜7)=X_(0˜7) to calculate s₆ and store s₆ in R₆ of the 1T1R arrayG₃; when c₆=0, s₆=a₆⊕b₆, and when c₅=1, s₆=a₆⊕b₆ .

(S5-9) Inputting logic signals V_(WL0c˜7c)=0, V_(WL8c)=1, V_(BL0c˜8c)=a₇and V_(SL0c˜8c)==b₇ to calculate c₈=a₇·b₇+a₇·c₇+c₇·b₇ and store c₈ inR_(8c) of the 1T1R array G₂; inputting logic signals V_(WL0˜6)=0,V_(WL7)=c₇, V_(BL0˜7)=X_(0˜7) and V_(SL0˜7)=X_(0˜7) to calculate s₇ andstore s₇ in R₇ of the 1T1R array G₃; when c₇=0, s₇=a₇⊕b₇, and when c₇=1,s₇=a₇⊕b₇ .

FIG. 9 shows an operation circuit based on the computing array accordingto the present invention for implementing an 8-bit pre-calculationadder, in which sums s_(0˜7) and carry information c₈ are calculatedaccording to input data a_(0˜7) and b_(0˜7) and carry information c₀;the operation circuit includes a 1T1R array H₁ and a 1T1R array Hz; the1T1R array H₁ includes nine 1T1R devices R_(0c)˜R_(8c) for calculatingcarry data c_(i) (i is an integer from 0 to 8), word line controlsignals corresponding to R_(0c)˜R_(8c) are respectivelyV_(WL0c)˜V_(WL8c), bit line control signals corresponding toR_(0c)˜R_(8c) are respectively V_(BL0c)˜V_(BL8c), and source linecontrol signals corresponding to R_(0c)˜R_(8c) are respectivelyV_(SL0c)˜V_(SL8c); the 1T1R array H₂ includes eight 1T1R devices R₀˜R₇for calculating and storing addition operation results s_(0˜7), wordline control signals corresponding to R₀˜R₇ are respectivelyV_(WL0)˜V_(WL7), bit line control signals corresponding to R₀˜R₇ arerespectively V_(BL0)˜V_(BL7), and source line control signalscorresponding to R₀˜R₇ are respectively V_(SL0)˜V_(SL7); and the carryinformation c₁ calculated by the 1T1R array H₁ is converted by thesignal amplifier and the control signal modem, and then transmitted tothe 1T1R array H₂ through the data transmission circuit.

In conjunction with the operation circuit based on the computing arrayshown in FIG. 9, an operating method according to the present inventioncomprises the following steps.

(S6-1) Inputting logic signals V_(WL0c˜8c)=1, V_(BL0c˜8c)=c₀ andV_(SL0c˜8c)=c₀ to store c₀ in R_(0c)˜R_(8c) of the 1T1R array H₁;inputting logic signals V_(WL0˜7)=1, V_(BL0˜7)=c₀ and V_(SL0˜7)=c₀ tostore the input carry information c₀ in R₀˜R₇ of the 1T1R array H₂.

(S6-2) Inputting logic signals V_(WL0c)=0, V_(WL1c˜8c)=1, V_(BL0c˜8c)=a₀and V_(SL0c˜8c)=b₀ to calculate c₁=a₀·b₀+a₀·c₀+c₀·b₀ and store c₁ inR_(1c˜8c) of the 1T1R array H₁; inputting logic signals V_(WL0˜7)=1,V_(BL0˜7)=a₀, V_(SL0)=b₀ and V_(SL1˜7)=b₀ to calculate s₀′=c₀·a₀+c₀·a₀·b₀ +c₀·a₀ ·b₀ and c₁=a₀·b₀+a₀·c₀+c₀·b₀ and store s₀′ in R₀ of the1T1R array H₂ and c₁ in R₁˜R₇ of the 1T1R array H₂.

(S6-3) Inputting logic signals V_(WL0c˜1c)=0, V_(WL2c˜8c)=1,V_(BL0c˜8c)=a₁ and V_(SL0c˜8c)=b₁ to calculate c₂=a₁·b₁+a₁·c₁+c₁·b₁ andstore c₂ in R_(2c˜8c) of the 1T1R array H₁; inputting logic signalsV_(WL0˜7)=1, V_(BL0)=b₀, V_(BL1˜7)=a₁, V_(SL0)=c₁, V_(SL1)=b₁ andV_(SL2˜7)=b₁ to calculate s₀=a₀⊕b₀⊕c₀, s₁=c₁·a₁+c₁ ·a₁·b₁ +c₁·a₁ ·b₁ andc₂ and store s₀ in R₀ of the 1T1R array H₂, s₁′ in R₁ of the 1T1R arrayH₂ and c₂ in R₂˜R₇ of the 1T1R array H₂.

(S6-4) Inputting logic signals V_(WL0c˜2c)=0, V_(WL3c˜8c)=1,V_(BL0c˜8c)=a₂ and V_(SL0c˜8c)=b₂ to calculate c₃=a₂·b₂+a₂c₂+c₂·b₂ andstore c₃ in R_(3c˜8c) of the 1T1R array H₁; inputting logic signalsV_(WL0)=0, V_(WL1˜7)=1, V_(BL0=)0, V_(BL1)=b₁, V_(BL2˜7)a₂, V_(SL0)=0,V_(SL1)=c₂, V_(SL2)=b₂ and V_(SL3˜7)=b₂ to calculate s₁=a₁⊕b₁⊕c₁,s₂=c₂·a₂+c₂ ·a₂·b₂ +c₂·a₂ ·b₂ and c₃=a₂·b₂+a₂·c₂+c₂·b₂ and store s₁ inR₁ of the 1T1R array H₂, s₂ in R₂ of the 1T1R array H₂ and c₃ in R₃˜R₇of the 1T1R array H₂.

(S6-5) Inputting logic signals V_(WL0c˜3c)=0, V_(WL4c˜8c)=1,V_(BL0c˜8c)=a₃ and V_(SL0c˜8c)=b₃ to calculate c₄=a₃·b₃+a₃·c₃+c₃·b₃ andstore c₄ in R_(4c˜8c) of the 1T1R array H₁; inputting logic signalsV_(WL0˜1)=0, V_(WL2˜7)=1, V_(BL0˜1)=0, V_(BL2)=b₂, V_(BL3˜7)=a₃,V_(SL0˜1)=0, V_(SL2)=c₃, V_(SL3)=b₃ and V_(SL4˜7)=b₃ to calculates₂=a₂⊕b₂⊕c₂, s₃′=c₃·a₃+c₃ ·a₃·b₃ +c₃·a₃ ·b₃ and c₄, and store s₂ in R₂of the 1T1R array H₂, s₃′ in R₃ of the 1T1R array H₂ and c₄ in R₄˜R₇ ofthe 1T1R array H₂.

(S6-6) Inputting logic signals V_(WL0c˜4c)=0, V_(WL5c˜8c)=1,V_(BL0c˜8c)=a₄ and V_(SL0c˜8c)=b₄ to calculate c₅=a₄·b₄+a₄·c₄+c₄·b₄ andstore c₅ in R_(5c˜8c) of the 1T1R array H₁; inputting logic signalsV_(WL0˜2)=0, V_(WL3˜7)=1, V_(BL0˜2)=0, V_(BL3)=b₃, V_(BL4˜7)=a₄,V_(SL0˜2)=0, V_(SL3)=c₄, V_(SL4)=b₄ and V_(SL5˜7)=b₄ to calculates₃=a₃⊕b₃⊕c₃, s₄′=c₄·a₄+c₄ ·a₄·b₄ +c₄·a₄ ·b₄ and c₅, and store s₃ in R₃of the 1T1R array H₂, s₄′ in R₄ of the 1T1R array H₂ and c₅ in R₅˜R₇ ofthe 1T1R array H₂.

(S6-7) Inputting logic signals V_(WL0c˜5c)=0, V_(WL6c˜8c)=1,V_(BL0c˜8c)=a₅ and V_(SL0c˜8c)=b₅ to calculate c₆=a₅·b₅+a₅·c₅+c₅·b₅ andstore c₆ in R_(6c˜8c) of the 1T1R array H₁; inputting logic signalsV_(WL0˜3)=0, V_(WL4˜7)=1, V_(BL0˜3)=0, V_(BL4)=b₄, V_(BL5˜7)=a₅,V_(SL0˜3)=0, V_(SL4)=c₅, V_(SL5)=b₅ and V_(SL6˜7)=b₅ to calculates₄=a₄⊕b₄⊕c₄, s₅′=c₅·a₅+c₅ ·a₅·b₅ +c₅·a₅ ·b₅ and c₆, and store s₄ in R₄of the 1T1R array H₂, s₅′ in R₅ of the 1T1R array H₂ and c₆ in R₆˜R₇ ofthe 1T1R array H₂.

(S6-8) Inputting logic signals V_(WL0c˜6c)=0, V_(WL7c˜8c)=1,V_(BL0c˜8c)=a₆ and V_(SL0c˜8c)=b₆ to calculate c₇=a₆·b₆+a₆·c₆+c₆·b₆ andstore c₇ in R_(7c˜8c) of the 1T1R array H₁; inputting logic signalsV_(WL0˜4)=0, V_(WL5˜7)=1, V_(BL0˜4)=0, V_(BL5)=b₅, V_(BL6˜7)=a₆,V_(SL0˜4)=0, V_(SL5)=c₆, V_(SL6)=b₆ and V_(SL7)=b₆ to calculates₅=a₅⊕b₅⊕c₅, s₆′=c₆·a₆+c₆ ·a₆·b₆ +c₆·a₆ ·b₆ and c₇, and store s₅ in R₅of the 1T1R array H₂, s₆′ in R₆ of the 1T1R array H₂ and c₇ in R₇ of the1T1R array H₂.

(S6-9) Inputting logic signals V_(WL0c˜7c)=0, V_(WL8c)=1, V_(BL0c˜8c)=a₇and V_(SL0c˜8c)=b₇ to calculate c₈=a₇·b₇+a₇·c₇+c₇·b₇ and store c₈ inR_(8c) of the 1T1R array H₁; inputting logic signals V_(WL0˜5)=0,V_(WL6˜7)=1, V_(BL0˜5)=0, V_(BL6)=b₆, V_(BL7)=a₇, V_(SL0˜5)=0,V_(SL6)=c₇ and V_(SL7)=b₇ to calculate s₆=a₆⊕b₆⊕c₆ and s₇′=c₇·a₇+c₇·a₇·b₇ +c₇·a₇ ·b₇ , and store s₆ in R₆ of the 1T1R array H₂ and s₇′ inR₇ of the 1T1R array H₂.

(S6-10) Inputting logic signals V_(WL0˜6)=0, V_(WL7)=1, V_(BL0˜6)=0,V_(BL7)=b₇, V_(SL0˜6)=0 and V_(SL7)=c₈, and inputting a logic signal of0 to each of other terminals to calculate s₇=a₇⊕b₇⊕c₇ and store s₇ in R₇of the 1T1R array H₂.

It should be readily understood to those skilled in the art that theabove description is only preferred embodiments of the presentinvention, and does not limit the scope of the present invention. Anychange, equivalent substitution and modification made without departingfrom the spirit and scope of the present invention should be includedwithin the scope of the protection of the present invention.

What is claimed is:
 1. A computing array based on 1T1R device,comprising: one or more 1T1R arrays and a peripheral circuit; the 1T1Rarray is configured to achieve operation and storage of an operationresult, and the peripheral circuit is configured to transmit data andcontrol signals to control operation and storage processes of the 1T1Rarrays, wherein 16 basic Boolean logic operations are implemented bycontrolling initial resistance states of the 1T1R devices, word lineinput signals, bit line input signals and source line input signals; alogic signal stored in the 1T1R device is read by inputting a logicsignal V_(WL)=1 via a word line, a logic signal V_(BL)=V_(read) via abit line and a logic signal V_(SL)=0 via a source line; V_(read) is avoltage pulse signal applied when a resistance state of the 1T1R deviceis read.
 2. The computing array based on 1T1R device according to claim1, wherein the 1T1R array includes 1T1R devices arranged in an array,word lines WL, bit lines BL and source lines SL; resistance states ofthe 1T1R devices include: High Resistance H and Low Resistance L; the1T1R devices realize storage and processing of information throughdifferent resistance states; and the 1T1R devices in the same row areconnected to the same word line, the 1T1R devices in the same column areconnected to the same bit line and source line, and through applyingdifferent signals to the word lines WL, the bit lines BL and the sourcelines SL, different operations are achieved and operation results arestored.
 3. The computing array based on 1T1R device according to claim2, wherein the 1T1R device includes a transistor and a resistiveelement; the transistor includes a substrate, a source, a drain, aninsulating layer and a gate, in which the source is connected to thesource line SL, and the gate is connected to the word line WL; theresistive element includes two end electrodes, one of which is connectedto the bit line BL and the other of which is connected to the drain ofthe transistor; and the resistive element has a stacked structure with anonvolatile resistance transition characteristic.
 4. The computing arraybased on 1T1R device according to claim 2, wherein the peripheralcircuit includes: a state controller, a word line decoder, a source linedecoder, a bit line decoder, a signal amplifier, a control signal modemand a data transmission circuit; the state controller has a datainput/output terminal Data, an address input terminal Address, a clocksignal input terminal CLK, a result input terminal, a word line outputterminal, a bit line output terminal, a source line output terminal anda secondary output terminal; the data input/output terminal Data of thestate controller is configured to input calculated data on the one handand output a calculated result on the other hand, the address inputterminal Address of the state controller is configured to input addressinformation of a selected device, the clock signal input terminal CLK ofthe state controller is configured to input a clock signal forcontrolling a calculation timing, and the result input terminal of thestate controller is configured to input a calculated result generated bya pre-stage circuit; the state controller generates a control signalaccording to the input data, address information, clock signal andcalculated result, or outputs a final calculated result; an inputterminal of the word line decoder is connected to the word line outputterminal of the state controller, an output terminal of the word linedecoder is connected to the word line of the 1T1R array; the word linedecoder decodes the control signal generated by the state controller toobtain a word line control signal, and inputs the word line controlsignal to the 1T1R devices through the word line of the 1T1R array; aninput terminal of the bit line decoder is connected to the bit lineoutput terminal of the state controller, an output terminal of the bitline decoder is connected to the bit line of the 1T1R array; the bitline decoder decodes the control signal generated by the statecontroller to obtain a bit line control signal, and inputs the bit linecontrol signal to the 1T1R devices through the bit line of the 1T1Rarray; an input terminal of the source line decoder is connected to thesource line output terminal of the state controller, an output terminalof the source line decoder is connected to the source line of the 1T1Rarray; the source line decoder decodes the control signal generated bythe state controller to obtain a source line control signal, and inputsthe source line control signal to the 1T1R devices through the sourceline of the 1T1R array; the word line control signal, the bit linecontrol signal and the source line control signal are commonly appliedto the 1T1R array to control states of the 1T1R devices in the 1T1Rarray; an input terminal of the signal amplifier is connected to a bitline of the 1T1R array; when data information stored in the 1T1R arrayis read, the signal amplifier converts an acquired resistance signalstored by the 1T1R device into a voltage signal and then outputs it tothe control signal modern; a first input terminal of the control signalmodern is connected to the secondary output terminal of the statecontroller, a second input terminal of the control signal modem isconnected to an output terminal of the signal amplifier; the controlsignal modem decodes the control signal generated by the statecontroller to obtain a control signal of a next-stage circuit, ordirectly transmits the data voltage signal output by the signalamplifier; the next-stage circuit is the next 1T1R device in the same1T1R array, or a next 1T1R array in the compute array; an input terminalof the data transmission circuit is connected to an output terminal ofthe control signal modem; the data transmission circuit feeds back thedata voltage signal output by the control signal modem to the statecontroller through the result input terminal of the state controller, ortransmits the control signal output from the control signal modem to theword line decoder, the bit line decoder and the source line decoder ofthe next-stage circuit.
 5. The computing array based on 1T1R deviceaccording to claim 3, wherein the peripheral circuit includes: a statecontroller, a word line decoder, a source line decoder, a bit linedecoder, a signal amplifier, a control signal modem and a datatransmission circuit; the state controller has a data input/outputterminal Data, an address input terminal Address, a clock signal inputterminal CLK, a result input terminal, a word line output terminal, abit line output terminal, a source line output terminal and a secondaryoutput terminal; the data input/output terminal Data of the statecontroller is configured to input calculated data on the one hand andoutput a calculated result on the other hand, the address input terminalAddress of the state controller is configured to input addressinformation of a selected device, the clock signal input terminal CLK ofthe state controller is configured to input a clock signal forcontrolling a calculation timing, and the result input terminal of thestate controller is configured to input a calculated result generated bya pre-stage circuit; the state controller generates a control signalaccording to the input data, address information, clock signal andcalculated result, or outputs a final calculated result; an inputterminal of the word line decoder is connected to the word line outputterminal of the state controller, an output terminal of the word linedecoder is connected to the word line of the 1T1R array; the word linedecoder decodes the control signal generated by the state controller toobtain a word line control signal, and inputs the word line controlsignal to the 1T1R devices through the word line of the 1T1R array; aninput terminal of the bit line decoder is connected to the bit lineoutput terminal of the state controller, an output terminal of the bitline decoder is connected to the bit line of the 1T1R array; the bitline decoder decodes the control signal generated by the statecontroller to obtain a bit line control signal, and inputs the bit linecontrol signal to the 1T1R devices through the bit line of the 1T1Rarray; an input terminal of the source line decoder is connected to thesource line output terminal of the state controller, an output terminalof the source line decoder is connected to the source line of the 1T1Rarray; the source line decoder decodes the control signal generated bythe state controller to obtain a source line control signal, and inputsthe source line control signal to the 1T1R devices through the sourceline of the 1T1R array; the word line control signal, the bit linecontrol signal and the source line control signal are commonly appliedto the 1T1R array to control states of the 1T1R devices in the 1T1Rarray; an input terminal of the signal amplifier is connected to a bitline of the 1T1R array; when data information stored in the 1T1R arrayis read, the signal amplifier converts an acquired resistance signalstored by the 1T1R device into a voltage signal and then outputs it tothe control signal modem; a first input terminal of the control signalmodem is connected to the secondary output terminal of the statecontroller, a second input terminal of the control signal modem isconnected to an output terminal of the signal amplifier; the controlsignal modem decodes the control signal generated by the statecontroller to obtain a control signal of a next-stage circuit, ordirectly transmits the data voltage signal output by the signalamplifier; the next-stage circuit is the next 1T1R device in the same1T1R array, or a next 1T1R array in the compute array; an input terminalof the data transmission circuit is connected to an output terminal ofthe control signal modem; the data transmission circuit feeds back thedata voltage signal output by the control signal modem to the statecontroller through the result input terminal of the state controller, ortransmits the control signal output from the control signal modem to theword line decoder, the bit line decoder and the source line decoder ofthe next-stage circuit.
 6. The computing array based on 1T1R deviceaccording to claim 1, wherein the peripheral circuit includes: a statecontroller, a word line decoder, a source line decoder, a bit linedecoder, a signal amplifier, a control signal modern and a datatransmission circuit; the state controller has a data input/outputterminal Data, an address input terminal Address, a clock signal inputterminal CLK, a result input terminal, a word line output terminal, abit line output terminal, a source line output terminal and a secondaryoutput terminal; the data input/output terminal Data of the statecontroller is configured to input calculated data on the one hand andoutput a calculated result on the other hand, the address input terminalAddress of the state controller is configured to input addressinformation of a selected device, the clock signal input terminal CLK ofthe state controller is configured to input a clock signal forcontrolling a calculation timing, and the result input terminal of thestate controller is configured to input a calculated result generated bya pre-stage circuit; the state controller generates a control signalaccording to the input data, address information, clock signal andcalculated result, or outputs a final calculated result; an inputterminal of the word line decoder is connected to the word line outputterminal of the state controller, an output terminal of the word linedecoder is connected to the word line of the 1T1R array; the word linedecoder decodes the control signal generated by the state controller toobtain a word line control signal, and inputs the word line controlsignal to the 1T1R devices through the word line of the 1T1R array; aninput terminal of the bit line decoder is connected to the bit lineoutput terminal of the state controller, an output terminal of the bitline decoder is connected to the bit line of the 1T1R array; the bitline decoder decodes the control signal generated by the statecontroller to obtain a bit line control signal, and inputs the bit linecontrol signal to the 1T1R devices through the bit line of the 1T1Rarray; an input terminal of the source line decoder is connected to thesource line output terminal of the state controller, an output terminalof the source line decoder is connected to the source line of the 1T1Rarray; the source line decoder decodes the control signal generated bythe state controller to obtain a source line control signal, and inputsthe source line control signal to the 1T1R devices through the sourceline of the 1T1R array; the word line control signal, the bit linecontrol signal and the source line control signal are commonly appliedto the 1T1R array to control states of the 1T1R devices in the 1T1Rarray; an input terminal of the signal amplifier is connected to a bitline of the 1T1R array; when data information stored in the 1T1R arrayis read, the signal amplifier converts an acquired resistance signalstored by the 1T1R device into a voltage signal and then outputs it tothe control signal modem; a first input terminal of the control signalmodem is connected to the secondary output terminal of the statecontroller, a second input terminal of the control signal modem isconnected to an output terminal of the signal amplifier; the controlsignal modem decodes the control signal generated by the statecontroller to obtain a control signal of a next-stage circuit, ordirectly transmits the data voltage signal output by the signalamplifier; the next-stage circuit is the next 1T1R device in the same1T1R array, or a next 1T1R array in the compute array; an input terminalof the data transmission circuit is connected to an output terminal ofthe control signal modem; the data transmission circuit feeds back thedata voltage signal output by the control signal modem to the statecontroller through the result input terminal of the state controller, ortransmits the control signal output from the control signal modem to theword line decoder, the bit line decoder and the source line decoder ofthe next-stage circuit.
 7. The computing array based on 1T1R deviceaccording to claim 6, wherein the data input/output terminal Data, theaddress input terminal Address and the clock signal input terminal CLKof the state controller respectively serve as a data input/outputterminal, an address input terminal and a clock signal input terminal ofthe computing array.
 8. An operation circuit based on the computingarray according to claim 6 for implementing a 1-bit full adder, in whicha sum s₀ and a high-order carry c₁ are calculated according to a logicsignal a, a logic signal b and a low-order carry c₀ that are input,comprising: a 1T1R array A₁, a 1T1R array A₂ and a 1T1R array A₃; the1T1R array A₁ includes a 1T1R device R_(b) for calculating and storingintermediate data s₀*, a word line signal corresponding to R_(b) isV_(WLb), a bit line signal corresponding to R_(b) is V_(BLh) and asource line signal corresponding to R_(b) is V_(SLb); the 1T1R array A₂includes a 1T1R device R_(c) for calculating and storing the high-ordercarry c₁, a word line signal corresponding to R_(c) is V_(WLC), a bitline signal corresponding to R, is V_(BLc), and a source line signalcorresponding to R_(c) is V_(SLc); the 1T1R array A₃ includes a 1T1Rdevice R_(s) for calculating and storing the sum s₀, a word line signalcorresponding to R_(s) is V_(WLs), a bit line signal corresponding toR_(s) is V_(BLs) and a source line signal corresponding to R_(s) isV_(SLs); and the intermediate data s₀* calculated by the 1T1R array A₁and the high-order carry c₁ calculated by the 1T1R array A₂ areconverted by the signal amplifier and the control signal modem, and thentransmitted to the 1T1R array A₃ through the data transmission circuit.9. An operating method based on the operation circuit according to claim8, comprising: (S1-1) inputting logic signals V_(WLc)=1, V_(BLc)=c₀ andV_(SLc)=c₀ to write the input logic signal c₀ into R_(c) of the 1T1Rarray A₂; inputting logic signals V_(WLb)=1, V_(BLb)=a₀ and V_(SLb)=a₀to write the input logic signal a₀ into R_(b) of the 1T1R array A₁;inputting logic signals V_(WLs)=1, V_(BLs)=a₀ and V_(SLs)=a₀ to writethe input logic signal a₀ into R_(s) of the 1T1R array A₃; (S1-2)inputting logic signals V_(WLc)=1, V_(BLc)=a₀ and V_(SLc)=b₀ tocalculate a high-order carry c₁=a₀·b₀+a₀·c₀+c₀·b₀ and store c₁ in R_(c)of the 1T1R array A₂; inputting logic signals V_(WLb)=b₀, V_(Blb)=a₀ andV_(SLb)=a₀ to calculate an intermediate result s₀*=a₀⊕b₀ and store s₀*in R_(b) of the 1T1R array A₁; inputting logic signals V_(WLs)=b₀,V_(BLs)=a₀ and V_(SLs)=a₀ to calculate an intermediate result s₀* andstore s₀* in R_(s) of the 1T1R array A₃; (S1-3) reading the logic signalc₁ stored in R_(c) of the 1T1R array A₂; reading the logic signal s₀*stored in R_(b) of the 1T1R array A₁; inputting logic signalsV_(WLs)=c₀, V_(BLs)=s₀* and V_(SLs)=s₀* to calculate a sum s₀=a₀⊕b₀⊕c₀and store s₀ in R_(s) of the 1T1R array A₃; and (S1-4) reading the logicsignal s₀ stored in R_(s) of the 1T1R array A₃.
 10. An operation circuitbased on the computing array according to claim 6 for implementing amulti-bit step-by-step carry adder, in which sums s_(0˜n−1) and carryinformation c_(n) are calculated according to input data a_(0˜n−1) andb_(0˜n−1) and carry information c₀, and n represents the number of bitsof the operation data, comprising: a 1T1R array D₁, a 1T1R array D₂ anda 1T1R array D₃; the 1T1R array D₁ includes n 1T1R devicesR_(0b)˜R_((n−1)b) for calculating and storing intermediate resultss_(0˜n−1)*, word line control signals corresponding to R_(0b)˜R_((n−1)b)are respectively V_(WL0b)˜V_(WL(n−1)b), bit line control signalscorresponding to R_(0b)˜R_((n−1)b) are respectively V_(BL(n−1)b) andsource line control signals corresponding to R_(0b)˜R_((n−1)b) arerespectively V_(sL0b)˜V_(SL(n−1)b); the 1T1R array D₁ is used for databackup; the 1T1R array D₂ includes a 1T1R device R_(n) for calculatingand storing carry data c_(i), i is an integer from 0 to 8, a word linecontrol signal corresponding to R_(n) is V_(WLn), a bit line controlsignal corresponding to R_(n) is V_(BLn) and a source line controlsignal corresponding to R_(n) is V_(SLn); the 1T1R array D₃ includes n1T1R devices R₀˜R_(n−1) for calculating and storing addition operationresults s_(0˜n−1), word line control signals corresponding to R₀˜R_(n−1)are respectively V_(WL0)˜V_(WL(n−1)), bit line control signalscorresponding to R₀˜R_(n−1) are respectively V_(BL0)˜V_(BL(n−1)), andsource line control signals corresponding to R₀˜R_(n−1) are respectivelyV_(sL0)˜V_(SL(n−1)); and the intermediate data s_(0˜n−1)*calculated bythe 1T1R array D₁ and the carry information c_(i) calculated by the 1T1Rarray D₂ are converted by the signal amplifier and the control signalmodem, and then transmitted to the 1T1R array D₃ through the datatransmission circuit.
 11. An operating method based on the operationcircuit according to claim 9, comprising: (S2-1) inputting logic signalsV_(WL0˜(n−1))=1, V_(BL0˜(n−1))=a_(0˜n−1) and V_(SL0˜(n−1))=a_(0˜n−1) towrite the input data a_(0˜n−1) into R_(0˜n−1) of the 1T1R array D₃;inputting logic signals V_(WLn)=1, V_(BLn)=c₀ and V_(SLn)=c₀ to writethe carry information c₀ into R_(n) of the 1T1R array D₂, a word lineinput signal, a bit line input signal and a source line input signal ofthe 1T1R array D₁ being the same as that of the 1T1R array D₃; (S2-2)inputting logic signals V_(WL0˜(n−1))=b_(0˜n−1), V_(BL0˜(n−1))=a_(0˜n−1)and V_(SL0˜(n−1))=a_(0˜n−1) to calculate intermediate resultss_(0˜n−1)*=a_(0˜n−1)⊕b_(0˜n−1) and store s_(0˜n−1)*, in R_(0˜n−1) of the1T1R array D₃; inputting logic signals V_(WL0b˜(n−1)b)=b_(0˜n−1),V_(BL0b˜(n−1)b)=a_(0˜n−1) and V_(SL0b)˜_((n−1)b)=a_(0˜-n−1) to calculateintermediate results s_(0˜n−1)* and store s_(0˜n−1)* in R_(0b˜(n−1)b) ofthe 1T1R array D₁; inputting logic signals V_(WLn˜)=1, V_(BLn)=a₀ andV_(SLn)=b₀ to calculate c₁=a₀·b₀+a₀·c₀+c₀·b₀ and store c₁ in R_(n) ofthe 1T1R array D₂; (S2-3) reading s₀* from R_(0b) of the 1T1R array D₁,and reading s₁* from R_(1b) of the 1T1R array D1; inputting logicsignals V_(WL0)=c₀, V_(WL1)=c₁, V_(WL2˜n−1)=0, V_(BL0)=s₀*, V_(BL1)=s₁*,V_(BL2˜n−1)=0, V_(SL0)=s₀*, V_(SL1)=s₁* and V_(SL2˜n−1)=0 to calculates₀=a₀⊕b₀⊕c₀ and s₁=a₁⊕b₁⊕c₁, and store s₀ in R₀ of the 1T1R array D₃ ands₁ in R₁ of the 1T1R array D₃; (S2-4) denoting the i-th bit in theoperation data or operation result by i, and giving i an initial valueof i=2; (S2-5) inputting logic signals V_(WLn=1), V_(BLn)=a_(i−1) andV_(SLn)=b_(i−1) , to calculatec_(i)=a_(i−1)·b_(i−1)+a_(i−1)·c_(i−1)+c_(i−1)·b_(i−1) and store c_(i) inR_(n) of the 1T1R array D₂; (S2-6) reading from R_(ib) of the 1T1R arrayD₁; inputting logic signals V_(WL0˜(i−1))=0, V_(WLi)=c_(i),V_(WL(i+1)˜(n−1))=0, V_(BL0˜(i−1))=0, V_(BLi)=s_(i)*,V_(BL(i+1)˜(n−1))=0, V_(SL0˜(i−1))=0, V_(SLi)=s_(i)* andV_(SL(i+1)˜(n−1))=0 to calculate s_(i)=a_(i)⊕b_(i)⊕c_(i) and store s_(i)in R_(i) of the 1T1R array D₃; (S2-7) incrementing the value of i by 1,and if i<n−1, proceeding to the step (S2-5); otherwise, proceeding tostep (S2-8); (S2-8) inputting logic signals V_(WLn)=1, V_(BLn)=a_(n−2)and V_(SLn)=b_(n−2) to calculatec_(n−1)=a_(n−2)·b_(n−2)+a_(n−2)·c_(n−2)+c_(n−2)·b_(n−2) and storec_(n−1) in R of the 1T1R array D₂; (S2-9) reading s_(n−1)* fromR_((n−1)b) of the 1T1R array D₁; inputting logic signalsV_(WL0˜(n−2))=0, V_(WL(n−1))=c_(n−1), V_(BL0˜(n−2))=0,V_(BL(n−1))=s_(n−1)*, V_(SL0˜(n−2))=0, and V_(SL(n−1))=s_(n−1)* tocalculate s_(n−1)=a_(n−1) ⊕b_(n−1)⊕c_(n−1) and store s_(n−1) in R_(n−1)of the 1T1R array D₃; and (S2-10) inputting logic signals V_(WLn)=1,V_(BLn)=a_(n−1) and V_(SLn)=b_(n−1) to calculatec_(n)=a_(n−1)·b_(n−1)+a_(n−1)·c_(n−1)+c_(n−1)·b_(n−1) and store c_(n) inR_(n) of the 1T1R array D₂.
 12. An operation circuit based on thecomputing array according to claim 6 for implementing an optimizedmulti-bit step-by-step carry adder, in which sums s_(0˜n−1) and carryinformation c_(n) are calculated according to input data a_(0˜n−1) andb_(0˜n−1) and carry information c₀, and n represents the number of bitsof the operation data, comprising: a 1T1R array E₁, a 1T1R array E₂ anda 1T1R array E₃; the 1T1R array E₁ includes n 1T1R devicesR_(0b)˜R_((n−1)b) for calculating and storing data s_(0˜n−1)*, word linecontrol signals corresponding to R_(0b)˜R_((n−1)b) are respectivelyV_(WL0b)˜V_(WL(n−1)b), bit line control signals corresponding toR_(0b)˜R_((n−1)b) are respectively V_(BL0b)˜V_(BL(n−1)b), and sourceline control signals corresponding to R_(0b)˜R_((n−1)b) are respectivelyV_(SL0b)˜V_(SL(n−1)b); the 1T1R array E₁ is used for data backup; the1T1R array E₂ includes (n+1) 1T1R devices R_(0c)˜R_(nc) for calculatingand storing carry data c_(i), i is an integer from 0 to n, word linecontrol signals corresponding to R_(0c)˜R_(nc) are respectivelyV_(WL0c)˜V_(WLnc), bit line control signals corresponding toR_(0c)˜R_(nc) are respectively V_(BL0c)˜V_(BLnc), and source linecontrol signals corresponding to R_(0c)˜R_(nc) are respectivelyV_(SL0c)˜V_(SLnc); the 1T1R array E₃ includes n 1T1R devices R₀˜R_(n−1)for calculating and storing addition operation results s_(0˜n−1), wordline control signals corresponding to R₀˜R_(n−1) are respectivelyV_(WL0)˜V_(WL(n−1)), bit line control signals corresponding toR₀˜R_(n−1) are respectively V_(BL0)˜V_(BL(n−1)), and source line controlsignals corresponding to R₀˜R_(n−1) are respectivelyV_(sL0)˜V_(SL(n−1)); and the intermediate data s_(0˜n−1)* calculated bythe 1T1R array E₁ and the carry information c_(i) calculated by the 1T1Rarray E₂ are converted by the signal amplifier and the control signalmodem, and then transmitted to the 1T1R array E₃ through the datatransmission circuit.
 13. An operating method based on the operationcircuit according to claim 12, comprising: (S3-1) inputting logicsignals V_(WL0˜(n−1))=1, V_(BL0˜(n−1))=a_(0˜n−1) andV_(SL0˜(n−1))=a_(0˜n−1) to write the input operational data a_(0˜n−1)into R_(0˜n−1) of the 1T1R array E₃; inputting logic signalsV_(WL0b˜(n−1)b)=1, V_(BL0b˜(n−1)b)=a_(0˜n−1) andV_(SL0b˜(n−1)b)=a_(0˜n−1) to write the input operational data a_(0˜n−1)into R_(0b˜(n−1)b) of the 1T1R array E₁; inputting logic signalsV_(WL0c˜nc)=1, V_(BL0c˜nc)=c₀ and V_(SL0c˜nc)=c₀ to write the carryinformation c₀ into R_(0c˜nc) of the 1T1R array E₂; (S3-2) inputtinglogic signals V_(WL0˜(n−1))=b_(0˜n−1), V_(Bl0˜(n−1))=a_(0˜n−1) andV_(SL0˜(n−1))=a_(0˜n−1) to calculate intermediate resultss_(0˜n−1)*=a_(0˜n−1)⊕b_(0˜n−1) and store s_(0˜n−1)* in R_(0b˜(n−1)b) ofthe 1T1R array E₃; inputting logic signals V_(WL0b˜(n−1)b)=b_(0˜n−1),V_(BL0b˜(n−1)b)=a_(0˜n−1) and V_(SL0b˜(n−1)b)=a_(0˜n−1) to calculateintermediate results s_(0˜n−1)* and store s_(0˜n−1)* in R_(0b˜(n−1)b) ofthe 1T1R array E₁; inputting logic signals V_(WL0c)=0, V_(WL1c˜nc)=1,V_(BL0c˜nc)=a₀ and V_(SL0c˜nc)=b₀ to calculate c₁=a₀·b₀+a₀·c₀+c₀ b₀ andstore c₁ in R_(1c˜nc) of the 1T1R array E₂; (S3-3) reading s₀* fromR_(0b) of the 1T1R array E₁, and reading s₁* from R_(1b) of the 1T1Rarray E1; inputting logic signals V_(WL0)=c₀, V_(WL1)=c₁,V_(WL2˜(n−1))=0, V_(BL0)=s₀*, V_(BL1)=s₁*, V_(BL2˜(n−1))=0, V_(SL0)=s₀*,V_(SL1)=s₁* and V_(SL2˜(n−1))=0 to calculate s₀=a₀⊕b₀⊕c₀ and s₁=a₁⊕b₁⊕c₁and store s₀ in R₀ of the 1T1R array E₃ and s₁ in R₁ of the 1T1R arrayE₃; inputting logic signals V_(WL0c˜1c)=0, V_(WL2c˜nc)=1, V_(BL0c˜nc)=a₁and V_(SL0c˜nc)=b₁ to calculate c₂=a₁·b₁+a₁·c₁+c₁·b₁, and store c₂ ofthe 1T1R array E₂, (S3-4) denoting the i-th bit in the operation data oroperation result by i, and giving i an initial value of i=2; (S3-5)reading s_(i)* from R_(ib) of the 1T1R array E₁; inputting logic signalsV_(WL0˜(i−1))=0, V_(WLi)=c_(i), V_(WL(i+1)˜(n−1))=0, V_(BL0˜(i−1))=0,V_(BLi)=s_(i)*, V_(BL(i+1)˜(n−1))=0, V_(SL0˜(i−1))=0, V_(SLi)=s_(i)* andV_(SL(i+1)˜(n−1)=)0 to calculate s_(i)=a_(i)⊕b_(i)⊕c_(i), and stores_(i) in R_(i) of the 1T1R array E₃; inputting logic signalsV_(WL0c˜ic)=0, V_(WL(i+1)c˜nc)=1, V_(BL0c˜nc)=a_(i); andV_(SL0c˜nc)=b_(i) to calculatec_(i+1)=a_(i)·b_(i)+a_(i)·c_(i)+c_(i)·b_(i) and store c_(i+1) inR_((i+1)c˜nc)=1, of array the 1T1R array E₂; (S3-6) incrementing thevalue of i by 1, and if i<n−1, proceeding to the step (S3-5); otherwise,proceeding to a step (S3-7); and (3-7) reading s_(n−1)* from R_((n−1)b)of the 1T1R array E₁; inputting logic signals V_(WL0˜(n−2))=0,V_(WL(n−1))=c_(n−1), V_(BL0˜(n−2))=0, V_(BL(n−1))=s_(n−1)*,V_(SL0˜(n−2))=0 and V_(SL(n−1))=s_(n−1)* to calculates_(n−1)=a_(n−1)⊕b_(n−1)⊕c_(n−1) and store s_(n−1) in R_(n−1) of the 1T1Rarray E₃; and inputting logic signals V_(WL0c˜(n−1)c)=0, V_(WLnc)=1,V_(BL0c˜nc)=a_(n−1) and V_(SL0c˜nc)=b_(n−1) to calculatec_(n)=a_(n−1)·b_(n−1)+a_(n−1)·c_(n−1)+c_(n−1)·b_(n−1) and store c_(n) inR_(nc) of the 1T1R array E₂.
 14. An operation circuit based on thecomputing array according to claim 6 for implementing a 2-bit dataselector, in which a logic signal a, a logic signal b and a controlsignal Sel are input to output the logic signal a or the logic signal bby controlling a value of the control signal Sel, comprising: a 1T1Rarray F, wherein the 1T1R array F includes one 1T1R device R, a wordline signal corresponding to R is V_(WL), a bit line signalcorresponding to R is V_(BL), and a source line signal corresponding toR is V_(sL).
 15. An operating method based on the operation circuitaccording to claim 14, comprising: (S4-1) inputting logic signalsV_(WL)=1, V_(BL)=a and V_(SL)=ā to initialize the 1T1R device R, andwrite the input logic signal a into R of the 1T1R array F; and (S4-2)inputting logic signals V_(WL)=Sel, V_(BL)=b and V_(SL)=b to input thelogic signal b and the control signal Sel so as to select an outputlogic signal out, wherein the logic signal a and the logic signal brepresent only two independent logic signals; when the control signalSel=0, the output signal out=a; and when the control signal Sel=1, theoutput signal out=b.
 16. An operation circuit based on the computingarray according to claim 6 for implementing a multi-bit carry selectadder, in which sums s_(0˜n−1) and carry information c_(n) arecalculated according to input data a_(0˜n−1) and b_(0˜n−1) and carryinformation c₀, n represents the number of bits of the operation data,and in the calculation process, according to the carry information ofeach bit, an XNOR operation result or an XOR operation result of thecorresponding bit of the operation data is selected as bit informationof the sum, comprising: a 1T1R array G₁, a 1T1R array G₂ and a 1T1Rarray G₃; the 1T1R array G₁ includes n 1T1R devices R_(0x)˜R_((n−1)x)for calculating and storing XNOR operation results of data a_(0˜n−1) andb_(0˜n−1) (X_(0˜n−1)=a_(0˜n−1) XNOR b_(0˜n−1)), word line controlsignals corresponding to R_(0x)˜R_((n−1)x) are respectivelyV_(WL0x)˜V_(WL(n−1)x), bit line control signals corresponding toR_(0x)˜R_((n−1)x), are respectively V_(BL0x)˜V_(WL(n−1)x), and sourceline control signals corresponding to R_(0x)˜R_((n−1)x), arerespectively V_(SL0x)˜V_(SL(n−1)x); the 1T1R array G₂ includes (n+1)1T1R devices R_(0c)˜R_(nc) for calculating carry data c_(i), i is aninteger from 0 to n, word line control signals corresponding toR_(0c)˜R_(nc) are respectively V_(WL0c)˜V_(WLnc), bit line controlsignals corresponding to R_(0c)˜R_(nc) are respectivelyV_(BL0c)˜V_(BLnc), and source line control signals corresponding toR_(0c)˜R_(nc) are respectively V_(SL0c)˜V_(SL0c); the 1T1R array G₃includes n 1T1R devices R₀˜R_(n−1) for calculating and storing additionoperation results s_(0˜n−1), word line control signals corresponding toR₀˜R_(n−1) are respectively V_(WL0)˜V_(WL(n−1)), bit line controlsignals corresponding to R₀˜R_(n−1) are respectivelyV_(BL0)˜V_(BL(n−1)), and source line control signals corresponding toR₀˜R_(n−1) are respectively V_(SL0)˜V_(SL(n−1)); and the XNOR operationresults X_(0˜n−1) calculated by the 1T1R array G₁ and the carryinformation c_(i) calculated by the 1T1R array G₂ are converted by thesignal amplifier and the control signal modem, and then transmitted tothe 1T1R array G₃ through the data transmission circuit.
 17. Anoperating method based on the operation circuit according to claim 16,comprising: (S5-1) inputting logic signals V_(WL0x˜(n−1)x)=1,V_(BL0x˜(n−1)x)=b_(0˜n−1) and V_(SL0x˜(n−1)x)=b_(0˜n−1) to store theresult b_(0˜n−1) of inverting the input operation data b_(0˜n−1) inR_(0x˜(n−1)x) of the 1T1R array G1; inputting logic signals V_(WL0c˜=1),V_(BL0˜nc)=c₀ and V_(SL0c˜nc)=c₀ to store c₀ in R_(0c˜nc) of the 1T1Rarray G₂; inputting logic signals V_(WL0˜(n−1))=1,V_(BL0˜(n−1))a_(0−n−1) and V_(SL0˜(n−1))=a_(0˜n−1) to store the inputoperational data a_(0˜n−1) in R_(0˜n−1) of the 1T1R array G₃; (S5-2)inputting logic signals V_(WL0x˜(n−1)x)=a_(0˜n−1),V_(BL0x˜(n−1)x)=b_(0˜n−1) and V_(SL0x˜(n−1)x)=b_(0˜n−1) to calculateXNOR operation results X_(0˜n−1)=a_(0˜n−1) XNOR b_(0˜n−1) of thecalculated data a_(0˜n−1) and b_(0˜n−1) and store X_(0˜n−1) inR_(0x˜(n−1)x) of the 1T1R array G₁; inputting logic signals V_(WL0c)=0,V_(WL1c˜nc)=1, V_(BL0c˜nc)=a₀ and V_(SL0c˜nc)=b₀ to calculatec₁=a₀·b₀+a₀·c₀+c₀·b₀ and store c₁ in R_(1c˜nc) of the 1T1R array G₂;inputting logic signals V_(WL0˜(n−1))=b_(0˜n−1), V_(BL0˜(n−1))=a_(0˜n−1)and V_(SL0˜(n−1))=a_(0˜n−1) to calculate XOR operation resultss_(0˜n−1)*=a_(0˜n−1)⊕b_(0˜n−1) and store s_(0˜n−1)* in R_(0˜n−1) of the1T1R array G₃; (S5-3) inputting logic signals V_(WL0c˜1c)=0,V_(WL2c˜nc)=1, V_(BL0c˜nc)=a₁ and V_(SL0c˜nc)=b₀ to calculatec₂=a₁·b₁+a₁·c₁+c₁·b₁ and store c₂ in R_(2c˜nc) of the 1T1R array G₂;inputting logic signals V_(WL0)=c₀, V_(WL1)=c₁, V_(WL2˜(n−1))=0,V_(BL0˜(n−1))=X_(0˜n−1) and V_(SL0˜(n−1))=X_(0˜n−1) to calculate s₀ ands₁, and store s₀ in R₀ of the 1T1R array G₃ and s₁ in R₁ of the 1T1Rarray G₃; when c₀=0, s₀=a₀⊕b₀, and when c₁=0, s₀=a₀⊕b₀ ; when c₁=0,s₁=a₁⊕b₁, and when c₁=1, s₁=a₁⊕b₁ ; (S5-4) denoting the i-th bit in theoperation data or operation result by i, and giving i an initial valueof i=2; (S5-5) inputting logic signals V_(WL0c˜ic)=0, V_(WL(i+1)c)=1,V_(BL0c˜nc)=a_(i) and V_(SL0c˜nc)=b_(i) to calculatec_(i+1)=a_(i)·b_(i)+a_(i)·c_(i)+c_(i)·b_(i) and store c_(i+1) inR_((i+1)c˜nc) of the 1T1R array G₂; inputting logic signalsV_(WL0˜(i−1))=0, V_(WLi)=c_(i), V_(WL(i+1)˜(n−1))=0,V_(BL0˜(n−1))=X_(0˜n−1) and V_(SL0˜(n−1))=X_(0˜n−1) to calculate s_(i)and store s_(i) in R_(i) of the 1T1R array G₃; when c_(i)=0,s_(i)=a_(i)⊕b_(i), and when c_(i)=1, s_(i)=a_(i)⊕b_(i) ; (S5-6)incrementing the value of i by 1, and if i<n−1, proceeding to the step(S5-5); otherwise, proceeding to a step (S5-7); and (S5-7) inputtinglogic signals V_(WL0c˜(n−1)c)=0, V_(WLnc)=1, V_(BL0˜nc)=a_(n−1) andV_(SL0c˜nc)=b_(n−1) to calculatec_(n)=a_(n−1)·b_(n−1)+a_(n−1)·c_(n−1)+c_(n−1)·b_(n−1) and store c_(n) inR_(nc) of the 1T1R array G₂; inputting logic signals V_(WL0˜(n−2))=0,V_(WL(n−1))=c_(n−1), V_(BL0˜(n−1))=X_(0˜n−1) and V_(SL0˜(n−1))=X_(0˜n−1)to calculate s_(n−1) and store s_(n−1) in R_(n−1) of the 1T1R array G₃;when c_(n−1)=0, s_(n−1)=a_(n−1) ⊕b_(n−1), and when c_(n−1)=1,s₇=a_(n−1)⊕b_(n−1) .
 18. An operation circuit based on the computingarray according to claim 6 for implementing a multi-bit pre-calculationadder, in which sums s_(0˜n−1) and carry information c_(n) arecalculated according to input data a_(0˜n−1) and b_(0˜n−1) and carryinformation c₀, and n represents the number of bits of the operationdata, comprising: a 1T1R array H₁ and a 1T1R array H₂; the 1T1R array H₁includes (n+1) 1T1R devices R_(0c)˜R_(nc) for calculating carry datac_(i), i is an integer from 0 to n, word line control signalscorresponding to R_(0c)˜R_(nc) are respectively V_(WL0c)˜V_(WLnc), bitline control signals corresponding to R_(0c)˜R_(nc) are respectivelyV_(BL0c)˜V_(BLnc), and source line control signals corresponding toR_(0c)˜R_(nc) are respectively V_(SL0c)˜V_(SLnc); the 1T1R array H₂includes n 1T1R devices R₀˜R_(n−1) for calculating and storing additionoperation results s_(0˜-n−1), word line control signals corresponding toR₀˜R_(n−1) are respectively V_(WL0)˜V_(WL(n−1)), bit line controlsignals corresponding to R₀˜R_(n−1) are respectivelyV_(BL0)˜V_(BL(n−1)), and source line control signals corresponding toR₀˜R_(n−1) are respectively V_(SL0)˜V_(SL(n−1)); and the carryinformation c_(i) calculated by the 1T1R array H₁ is converted by thesignal amplifier and the control signal modem, and then transmitted tothe 1T1R array H₂ through the data transmission circuit.
 19. Anoperating method based on the operation circuit according to claim 18,comprising: (S6-1) inputting logic signals V_(WL0c˜nc)=1, V_(BL0c˜nc)=c₀and V_(SL0c˜nc)=c₀ to store c₀ in R_(0c˜nc) of the 1T1R array H₁;inputting logic signals V_(WL0˜(n−1))=1, V_(BL0˜(n−1))=c₀ andV_(SL0˜(n−1))=c₀ to store the input carry information c₀ in R_(0˜n−1) ofthe 1T1R array H₂; (S6-2) inputting logic signals V_(WL0c)=0,V_(WL1c˜nc)=1, V_(BL0c˜nc)=a₀ and V_(SL0c˜nc)=b₀ to calculatec₁=a₀·b₀+a₀·c₀+c₀·b₀ and store c₁ in R_(1c˜nc) of the 1T1R array H₁;inputting logic signals V_(WL0˜(n−1))=1, V_(BL0˜(n−1))=a₀, V_(SL0)=b₀and V_(SL1˜(n−1)) b₀ to calculate s₀=c₀·a₀+c₀ ·a₀·b₀ +c₀·a₀ ·b₀ andc₁=a₀·b₀+a₀·c₀+c₀·b₀, and store s₀* in R₀ of the 1T1R array H₂ and c₁ inR_(1˜n−1) of the 1T1R array H₂; (S6-3) inputting logic signalsV_(WL0c˜1c)=0, V_(WL2c˜nc)=1, V_(BL0c˜nc)=a₁ and V_(SL0c˜nc)=b₁ tocalculate c₂=a₁·b₁+a₁·c₁+c₁·b₁ and store c₂ in R_(2c˜nc) of the 1T1Rarray H₁; inputting logic signals V_(WL0˜(n−1))=1, V_(BL0)=b₀,V_(BL1˜(n−1))=a₁, V_(SL0)=c₁, V_(SL1)=b₁ and V_(SL2˜(n−1)), b₁ tocalculate s₀=a₀⊕b₀⊕c₀, s₁=c₁·a₁+c₁ ·a₁·b₁ +c₁·a₁ ·b₁ andc₂=a₁·b₁+a₁·c₁+c₁·b₁, and store s₀ in R₀ of the 1T1R array H₂, s₁ in R₁of the 1T1R array H₂ and c₂ in R_(2˜(n−1)) of the 1T1R array H₂; (S6-4)denoting the i-th bit in the operation data or operation result by i,and giving i an initial value of i=1; (S6-5) inputting logic signalsV_(WL0c˜(i+1)c)=0, V_(WL(i+2)c˜nc)=1, V_(BL0c˜nc)=a_(i+1) andV_(SL0c˜nc)=b_(i+1) to calculatec_(i+2)=a_(i+1)·b_(i+1)+a_(i+1)·c_(i+1)+c₁₊₁·b_(i+1) and store c_(i+2)in R_((i+2)c˜nc) of the 1T1R array H₁; inputting logic signalsV_(WL0˜(i−1))=0, V_(WLi˜(n−1))=1, V_(BL0˜(i−1))=0, V_(BLi)=b_(i),V_(BL(i+1)˜(n−1))=a_(i+1), V_(SL0˜(i−1))=0, V_(SLi)=c_(i+1),V_(SL(i+1))=b_((i+1)) and V_(SL(i+2)˜(n−1))=b_(i+1) to calculates_(i)=a_(i)⊕b_(i)⊕c_(i), s_(i+1)=c_(i+1)·a_(i+1)+c_(i+1)·a_(i+1)·b_(i+1) +c_(i+1) a_(i+1) ·b_(i+1) andc_(i+2)=a_(i+1)·b_(i+1)+a_(i+1)·c_(i+1)+c_(i+1)·b_(i+1) and store s_(i)in R_(i) of the 1T1R array H₂, in R_(i+1) of the 1T1R array H₂ andc_(i+2) in R_((i+2)˜(n−1)) of the 1T1R array H₂; (S6-6) incrementing thevalue of i by 1, and if i<n−1, proceeding to the step (S6-5); otherwise,proceeding to a step (S6-7); (S6-7) inputting logic signalsV_(WL0c˜(n−1)c)=0, V_(WLnc)=1, V_(BL0c˜nc)=a_(n−1) andV_(SL0c˜nc)=b_(n−1) to calculatec_(n)=a_(n−1)·b_(n−1)+a_(n−1)·c_(n−1)+c_(n−1)·b_(n−1) and store c_(n) inR_(nc) of the 1T1R array H₁; inputting logic signals V_(WL0˜(n−3))=0,V_(WL(n−2)˜(n−1))=1, V_(BL0˜(n−3))=0, V_(BL(n−2))=b_(n−2),V_(BL(n−1))=a_(n−1), V_(SL0˜(n−3))=0, V_(SL(n−2))=c_(n−1) andV_(SL(n−1))=b_(n−1) to calculate s_(n−2)=a_(n−2)⊕b_(n−2)⊕c_(n−2) ands_(n−1)=c_(n−1)·a_(n−1)+c_(n−1) ·a_(n−1)·b_(n−1) +c_(n−1) and stores_(n−2) in R_(n−2) of the 1T1R array H₂ and s_(n−1)′, in R_(n−1) of the1T1R array H₂; and (S6-8) inputting logic signals V_(WL0˜(n−2))=0,V_(WL(n−1))=1, V_(BL0˜(n−2))=0, V_(BL(n−1))=b_(n−1), V_(SL0˜(n−2))=0 andV_(SL(n−1))=c_(n) to calculate s_(n−1)=a_(n−1) ⊕B_(n−1)⊕c_(n−1) andstore s_(n−1) in R_(n−1) of the 1T1R array H₂.